Continuous Bitstream Bus Protocol for Automotive Jitter Reduction

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Solution Overview

Problem

Current communication systems in automotive environments face challenges in providing reliable and low-jitter data transmission between a master device and multiple slave devices, particularly in harsh conditions, with existing protocols often resulting in latency and misalignment issues.

Innovation Solution

A digital communication system utilizing a continuous bitstream protocol that allows a master device to impose timing on a digital bus, reducing jitter by using a periodic signal for synchronization and avoiding bus collisions, with each slave device monitoring and aligning with the bitstream to transmit data in a bit-synchronous manner, and employing standard UARTs or USARTs for implementation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If asynchronous communication protocols (I2C, RS232) are used between master and slave devices, then communication flexibility is improved, but jitter between subsequent transmissions increases

Engineering Contradiction:
Improvecommunication flexibilityVSAvoidjitter between transmissions
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The master device transmits a continuous bitstream with periodic synchronization patterns at defined intervals, creating regular timing cycles that synchronize slave devices. This periodic structure ensures that data transmissions occur at predictable time intervals, reducing jitter while maintaining protocol flexibility through configurable frame formats and multiple slave support.

Inventive Principle:
Principle #19Periodic action

2Adaptability or versatility

If multiple slave devices communicate on the same bus without master timing control, then device independence is improved, but timing alignment and synchronization deteriorate

Engineering Contradiction:
Improvedevice independenceVSAvoidtiming alignment
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The master device acts as an intermediary that generates and transmits a continuous synchronized bitstream containing timing reference patterns. Slave devices independently process this bitstream to extract synchronization information, allowing them to maintain independent operation while achieving precise timing alignment through the master's mediating timing signal.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If standard UARTs or USARTs are used for implementation, then ease of manufacture is improved, but communication reliability in harsh environments may worsen

Engineering Contradiction:
Improveimplementation simplicityVSAvoidcommunication reliability in harsh conditions
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system configures standard UART/USART devices with specific parameter settings including baud rate, data bits, stop bits, and parity bits to optimize performance for automotive environments. The continuous bitstream protocol with synchronization patterns and error detection mechanisms modifies the operational parameters of standard components to achieve reliable communication in harsh conditions while maintaining ease of manufacture.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3629525B1Method and system for communicating over a bus
Publication Date: 2022.08.17 MELEXIS TECHNOLOGIES SA
  • EP3629525B1 patent drawingFigure 1
  • EP3629525B1 patent drawingFigure 2
  • EP3629525B1 patent drawingFigure 3

AI summary

A communication system (400) comprising: a digital serial bus (495), and a master device (490) and at least one slave device (410) connected to said bus; wherein the master and the slave(s) are adapted to communicate according to a predefined communication protocol; wherein the master is adapted for transmitting a continuous bitstream in the form of a plurality of frames, each frame comprising one or more words, each word having a constant time duration, the first word (SOF) of each frame being a unique word transmitted by the master for indicating the start of a frame; one or more bits (Sr) of each word being transmitted by the master as a dominant bit; a non-dominant bit, for allowing the at least one slave to overwrite; the at least one slave adapted for overwriting in the continuous bitstream some non-dominant bits to transmit data in a quasi-synchronous manner.