Continuous Channel 3D CMOS Transistor Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication nodes, traditional two-dimensional (2D) circuit scaling faces challenges due to manufacturing variability and electrostatic limitations, limiting transistor density and wire pitch scaling, making three-dimensional (3D) integration necessary to continue semiconductor scaling.
Innovation Solution
The implementation of continuous channels between 3D CMOS devices allows for reduced layout size, integration of buried power rails, and stacking of multiple CMOS planes, enabling increased transistor density and efficient 3D logic by forming continuous channels between side-by-side field effect transistors (FETs), which eliminates one connection and increases source/drain areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional 2D circuit scaling is used, then manufacturing process simplicity is maintained, but transistor density and wire pitch scaling are limited due to manufacturing variability and electrostatic device limitations
Solution Approach 1:
The patent transitions from traditional 2D planar transistor layouts to 3D vertically stacked transistor configurations. Multiple transistor layers are stacked above each other, enabling increased transistor density by utilizing the vertical dimension rather than only horizontal scaling, thereby overcoming the limitations of 2D scaling while managing fabrication complexity through systematic process integration.
2Productivity
If 3D vertically stacked transistors are implemented, then transistor density in volume is increased, but fabrication process complexity increases due to repeated film-forming depositions, etch mask creation, patterning, and doping treatments
Solution Approach 1:
The fabrication process is divided into discrete modular layers, with each layer undergoing specific sequences of deposition, patterning, and doping operations. This segmentation allows for systematic control of complex 3D structure formation, enabling independent optimization of each layer's fabrication while building toward the final high-density 3D transistor stack.
Solution Approach 2:
Support structures, sacrificial layers, and preliminary patterning features are formed in advance before the final transistor active regions are created. These preliminary structures guide subsequent fabrication steps and enable precise formation of the 3D stacked transistor geometry, simplifying the overall manufacturing process by pre-establishing the structural framework.
3Area of stationary object
If connection spaces between transistors are reduced in 3D stacks, then layout size is reduced, but manufacturing precision requirements increase due to tighter tolerances in aligning continuous channels between adjacent transistors
Solution Approach 1:
Shared continuous channel structures serve as intermediary elements that physically and electrically connect adjacent transistors while providing self-alignment references. These continuous channels act as mediating structures that reduce the need for separate connection elements, thereby reducing layout area while simultaneously providing alignment cues that relax manufacturing precision requirements through inherent self-registration.
Data Source
AI summary
A semiconductor device includes a first n-type transistor and a first p-type transistor that are positioned side by side over a substrate. The first n-type transistor includes a first n-type source/drain (S/D) region, a first n-type channel region, and a second n-type S/D region that are formed based on a first continuous channel structure extending along a horizontal direction parallel to the substrate. The first n-type channel region is positioned between the first n-type S/D region and the second n-type S/D region. The first p-type transistor includes a first p-type S/D region, a first p-type channel region, and a second p-type S/D region that are formed based on the first continuous channel structure. The first p-type channel region is positioned between the first p-type S/D region and the second p-type S/D region. The second n-type S/D region is in contact with the first p-type S/D region.