Continuous Fin Dummy Gate Layout for Transistor Leakage Blocking
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Solution Overview
Problem
In semiconductor manufacturing, the integration of transistors with dummy gate electrodes between source and drain regions leads to potential leakage due to differing voltage potentials, which existing approaches often address by increasing chip area through the use of filler cells, rather than modifying the threshold voltage of dummy gate transistors.
Innovation Solution
An auto-place and route tool modifies the layout to increase the threshold voltage of dummy gate transistors without altering the chip's footprint, ensuring reduced current leakage by configuring the dummy gate electrodes to always turn 'OFF' and prevent current flow between adjacent transistors with different threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gate electrodes are placed between source and drain regions to separate transistors, then transistor isolation is improved, but current leakage occurs due to differing voltage potentials
Solution Approach 1:
The patent changes the threshold voltage parameter of the dummy gate transistor to be higher than both adjacent transistors. This parameter modification ensures the dummy gate remains in an 'OFF' state during normal operation, effectively blocking current leakage while maintaining proper transistor isolation. The threshold voltage is increased through adjusted doping concentration in the dummy gate channel region.
2Loss of energy
If filler cells are used to address leakage, then leakage reduction is achieved, but chip area increases
Solution Approach 1:
Instead of adding filler cells that increase chip area, the patent modifies the threshold voltage parameter of the existing dummy gate transistor. This parameter change enables the dummy gate to function as an effective leakage barrier without requiring additional space, thus reducing leakage while maintaining compact chip layout.
3Productivity
If multiple transistors share a same continuous fin, then integration density is improved, but leakage between transistors increases
Solution Approach 1:
The patent applies local quality by creating a dummy gate transistor with distinct properties (higher threshold voltage) at a specific location between adjacent transistors on the same continuous fin. This localized modification with different doping concentration and threshold voltage enables effective leakage blocking at the critical interface region while allowing high integration density elsewhere.
4Ease of manufacture
If dummy gate transistor has standard threshold voltage, then manufacturing simplicity is maintained, but leakage prevention is insufficient
Solution Approach 1:
The patent modifies the threshold voltage parameter of the dummy gate transistor by adjusting the doping concentration in its channel region. This parameter change enhances leakage prevention capability while maintaining compatibility with existing manufacturing processes, as the doping adjustment can be integrated into standard fin formation and gate fabrication steps.
Data Source
AI summary
In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin over the substrate. Further, a doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second portion and the third portion of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.