Continuous Fin SRAM for LOD Stability
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Solution Overview
Problem
The performance of finFET-based SRAM cells is affected by the length of oxide diffusion (LOD) effect due to interrupted fin structures by isolation structures, leading to instability and increased soft error rates, which complicates the design and operation of memory arrays.
Innovation Solution
The fin structures in SRAM cells are designed to continuously extend across the memory array without interruption by isolation structures, using a combination of strained and unstrained semiconductor materials for the active structures, and optimizing transistor configurations to improve field effect mobility and reduce the need for additional patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional patterning processes are added to maintain fin continuity, then active structure uniformity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The shallow trench isolation layer is formed beforehand to establish a stopping barrier that prevents the isolation structure from interrupting the fin structures. This preliminary action ensures fin continuity is maintained without requiring additional patterning steps later in the manufacturing process.
Solution Approach 2:
The isolation structure automatically adjusts its depth to stop at the shallow trench isolation layer, which serves as a self-regulating barrier. This self-service mechanism eliminates the need for complex additional patterning processes to maintain fin continuity.
Data Source
AI summary
A memory array and a semiconductor chip are provided. The memory array includes memory cells, each includes: first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. A source/drain of the first pull-up transistor is coupled to a source/drain of the first pull-down transistor. A source/drain of the second pull-up transistor is coupled to a source/drain of the second pull-down transistor. Gates of the second pull-up and pull-down transistors are coupled to the first node. Gates of the first pull-up and pull-down transistors are coupled to the second node. The first and second pass-gate transistors are respectively coupled to the first and second nodes. The first and second pull-up transistors respectively include a first active structure having a bottom portion including a strained semiconductor material and a top portion including an unstrained semiconductor material. The first active structures continuously extend across the memory array.