Continuous-Time FIR Filter Cascade Without LC Equalizer Circuits
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Solution Overview
Problem
High-speed communication systems face challenges in implementing cost-effective continuous-time feedforward equalizers due to the expense of LC circuits, which are typically used for high-speed applications.
Innovation Solution
A continuous-time FIR filter is designed using a cascade topology of FIR cells with feedback and feedforward paths, each comprising delay and summing cells with differential circuit topologies, allowing for high-speed operation without the need for expensive LC circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LC circuits are used for high-speed continuous-time feedforward equalizers, then high-speed operation and good performance are achieved, but cost increases significantly
Solution Approach 1:
The equalizer is divided into multiple identical FIR cells, each handling a portion of the equalization task. This segmentation allows the system to achieve high-speed operation through parallel processing while using simpler, lower-cost circuitry in each cell, avoiding the need for expensive LC resonators in every stage.
Solution Approach 2:
Each FIR cell is designed as a universal building block that performs multiple functions: signal delay, weighted summation, and feedback processing. This multi-functionality eliminates the need for separate dedicated circuits for each operation, reducing overall system cost while maintaining high-speed continuous-time operation.
2Ease of operation
If discrete-time feedforward equalizers are used, then timing synchronization and automatic gain control are easier to implement, but high-speed sampling becomes very difficult to realize
Solution Approach 1:
The patent replaces the mechanical sampling process with a continuous-time signal processing approach. Instead of converting analog signals to discrete-time samples at high speeds (which is difficult), the system processes analog signals continuously through FIR cells, achieving both ease of control and high-speed operation simultaneously.
3Speed
If high-speed sampling devices are implemented, then discrete-time feedforward equalizers can operate at high speeds, but implementation difficulty and cost increase
Solution Approach 1:
The patent extracts the sampling function entirely from the system by operating in continuous-time domain. This removes the need for complex high-speed sampling devices and associated synchronization circuitry, significantly reducing implementation complexity while maintaining high-speed equalization capability.
Data Source
AI summary
A high-speed continuous-time FIR (finite impulse response) filter comprises a plurality of processing cells configured in a cascade topology. Each processing cell receives a first signal and a second signal from a preceding circuit and a succeeding circuit, respectively, and outputs a third signal and a fourth signal to the succeeding circuit and the preceding circuit, respectively. Each processing cell further comprises a delay cell and a summing cell. Each of the delay cell and the summing cell performs a high speed signal processing using a combination of a feedback loop and a feedforward path.