Continuous Gate And Fin Spacer Layout For Sub-10 Nm Scaling
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Solution Overview
Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or sub-10 nanometer node range, limiting further advancements due to variability and the need for new methodologies or technologies.
Innovation Solution
Implementing a pitch quartering approach for patterning semiconductor fins and integrating a three-layer trench isolation structure, along with differentiated gate and fin spacer designs, to enhance fabrication precision and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The fabrication process is divided into multiple discrete stages: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels and spacers, and repeating the process. This segmentation allows each stage to be optimized independently, achieving 10nm node precision through controlled sequential operations rather than attempting single-step patterning.
Solution Approach 2:
Mandrel structures are formed in advance at a relaxed pitch that is achievable with current lithography. These pre-formed mandrels serve as templates for subsequent spacer deposition, allowing the final fine-pitch features to be defined by spacer thickness rather than direct lithography, thereby achieving precision beyond the lithography limit.
2Productivity
If feature size is reduced to increase density, then productivity is improved, but manufacturing precision deteriorates due to variability
Solution Approach 1:
The patent replaces direct lithographic patterning (mechanical/optical system) with a spacer-based self-aligned patterning approach. The final feature dimensions are defined by conformal film deposition thickness rather than lithographic resolution, substituting a deposition process with more precise thickness control for the limiting patterning step, thereby achieving better feature size control at higher densities.
Solution Approach 2:
The critical dimension control is shifted from lithographic parameters (wavelength, numerical aperture) to deposition parameters (film thickness, conformality). By changing the controlling parameter from optical resolution to film thickness, the process achieves superior dimensional control at reduced feature sizes, enabling higher integration density without sacrificing precision.
3Manufacturing precision
If pitch quartering approach is implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of multiple fin structures into a unified continuous gate architecture. Rather than treating each fin as a separate device requiring individual gating, the gate is formed continuously across multiple fins, simplifying the overall structure while maintaining the precision benefits of pitch quartering for fin spacing and dimensions.
Solution Approach 2:
The continuous gate structure serves multiple functions simultaneously: it provides electrical control for multiple fins, acts as a unified patterning template for subsequent processing, and enables shared isolation structures between adjacent fin pairs. This multi-functionality reduces the number of separate components needed, offsetting the complexity introduced by pitch quartering.
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.