Continuous-Time Input Stage With Alternating DACs for Low-ISI ADCs
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Solution Overview
Problem
Conventional continuous time sigma delta ADCs suffer from accuracy degradation due to code transition glitches in the feedback DAC and intersymbol interference (ISI), which also reduce alias rejection, a critical feature of continuous time ADCs.
Innovation Solution
A continuous time input stage with a pair of alternating DACs and input resistors, where the input is always connected to the integrator, using switches to update DAC codes without disconnecting the input, thereby preventing ISI and maintaining anti-aliasing rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DAC is disconnected from integrators to update DAC codes, then DAC glitch errors are prevented from propagating to integrators, but alias rejection is greatly reduced
Solution Approach 1:
The single DAC is segmented into two separate DACs (first DAC and second DAC) that operate in alternating phases. This segmentation allows one DAC to be updated while the other remains connected to the integrator, preventing glitch propagation while maintaining continuous operation and alias rejection.
Solution Approach 2:
The system employs periodic action by alternating between two DACs in a phased manner. During each clock cycle, one DAC is connected to the integrator while the other is updated, and vice versa in the next phase. This periodic switching ensures that DAC updates occur without disconnecting the active DAC from the integrator, thereby maintaining alias rejection while preventing glitch errors.
2Object-generated harmful factors
If the input is disconnected to update DAC codes, then ISI is reduced, but anti-aliasing performance is degraded
Solution Approach 1:
The input stage is segmented into two parallel paths, each with its own DAC and input resistors. This allows one path to be updated while the other remains active and connected to the integrator, eliminating the need to disconnect the input and thereby preventing ISI while maintaining anti-aliasing performance.
Solution Approach 2:
The system maintains continuity of useful action by ensuring that the input remains continuously connected to the integrator through one of the two alternating DACs. This continuous connection preserves the anti-aliasing benefits of conventional continuous time ADCs while allowing updates to occur in the inactive DAC without causing ISI.
3Device complexity
If a single DAC is used and disconnected for updates, then device complexity is reduced, but linearity is degraded due to glitches
Solution Approach 1:
The single DAC is divided into two separate DACs that operate alternately. This segmentation allows one DAC to be updated without affecting the other, which remains connected and provides glitch-free feedback. The overall complexity increase is minimal compared to the significant improvement in linearity and accuracy.
Data Source
AI summary
A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.