Continuous Self-Refresh Timer for DRAM Power Optimization
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Solution Overview
Problem
Existing DRAM technologies face excessive power consumption due to unnecessary refresh operations when frequently entering and exiting self-refresh mode, as the status of refreshes is unknown and triggers refreshes upon each entry, leading to inefficient power management.
Innovation Solution
Implementing a continuous self-refresh timer that operates independently of entry and exit from self-refresh mode, allowing for power-saving self-refresh operations and subarray parallel refreshes by using a refresh control circuit that generates signals based on a self-refresh refresh time interval, enabling hidden refreshes and reducing unnecessary refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a refresh operation is triggered upon each entry into self-refresh mode, then data integrity is maintained, but power consumption increases due to unnecessary refresh operations
Solution Approach 1:
The patent implements a feedback mechanism where the refresh control circuit continuously monitors the self-refresh timer status and the self-refresh mode state. The circuit determines whether a refresh operation is actually needed by checking if the timer has expired and if the mode has been entered, preventing unnecessary refresh operations and reducing power consumption while maintaining data integrity.
Solution Approach 2:
The refresh control circuit autonomously determines when refresh operations are necessary by internally tracking timer expiration and mode entry status. This self-service approach eliminates the need for external controllers to manage refresh timing, allowing the system to intelligently suppress redundant refresh operations and optimize power consumption.
2Reliability
If conventional periodic refreshes are performed on an entire rank or bank, then data is refreshed reliably, but the entire rank or bank is prevented from handling requests during refresh
Solution Approach 1:
The patent segments the memory bank into multiple subarrays, allowing independent refresh operations on individual subarrays rather than requiring refresh of the entire bank. This segmentation enables other subarrays to continue handling read/write requests concurrently, maintaining productivity while ensuring reliable refresh of the targeted subarray.
Solution Approach 2:
Instead of performing complete bank-wide refresh operations, the patent implements partial refresh operations that target only specific subarrays or portions of the memory bank that require refreshing. This partial action approach maintains data reliability for refreshed portions while allowing the remaining portions to service requests normally.
Data Source
AI summary
Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.