Continuous Semiconductor Tester Operation During Multi-Stage Temperature Testing

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Solution Overview

Problem

Conventional semiconductor testing protocols at multiple temperatures result in significant index time due to ramping periods, leading to inefficiencies and increased total testing time, which hampers the throughput and effectiveness of automated test equipment and robotic handlers.

Innovation Solution

A methodology and system for continuous semiconductor testing at multiple temperatures during a single insertion sequence, where semiconductors are divided into subgroups and tested in parallel, substantially reducing or eliminating index time by optimizing temperature ramping and testing cycles, allowing for simultaneous execution of multiple temperature tests without interrupting the testing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional semiconductor testing protocols are used with sequential temperature ramping, then testing can be performed at multiple temperatures, but significant index time is incurred due to ramping periods between temperature changes

Engineering Contradiction:
Improvetesting temperatureVSAvoidindex time
Core Design Contradiction:
TemperatureVSLoss of time

Solution Approach 1:

The semiconductor devices are divided into multiple subgroups, and the testing process is segmented into parallel temperature testing sequences. Each subgroup is tested at a different temperature simultaneously, eliminating the need for sequential temperature ramping and the associated index time delays.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements continuous testing by maintaining multiple temperature testing sequences running in parallel simultaneously. This eliminates idle ramping periods between temperature changes, as the tester continuously performs useful testing operations across multiple subgroups at different temperatures without interruption.

Inventive Principle:
Principle #20Continuity of useful action

2Reliability

If multiple temperature tests are performed sequentially during a single insertion, then testing thoroughness is maintained, but total testing time increases due to repeated index time for each temperature transition

Engineering Contradiction:
Improvetesting thoroughnessVSAvoidtesting throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Devices are segmented into subgroups that can be tested in parallel at different temperatures. This segmentation allows thorough multi-temperature testing to be performed simultaneously on different subgroups rather than sequentially on the same devices, maintaining testing thoroughness while dramatically improving throughput by eliminating repeated index time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional sequential testing approach to a multi-dimensional parallel testing approach by introducing the dimension of simultaneous multi-temperature testing. Multiple temperature testing sequences execute in parallel across different subgroups, converting a time-sequential process into a spatially-parallel process that maintains thoroughness while boosting productivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If temperature ramping is performed between tests, then accurate temperature-specific testing is achieved, but equipment utilization decreases due to idle ramping periods

Engineering Contradiction:
Improvetemperature test accuracyVSAvoidequipment utilization
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system maintains continuous useful action by executing multiple temperature testing sequences in parallel simultaneously. While one subgroup is being tested at a specific temperature, other subgroups are being tested at different temperatures, eliminating idle ramping periods and maximizing equipment utilization while maintaining temperature test accuracy through dedicated temperature control for each parallel sequence.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The testing process is segmented into multiple independent temperature testing sequences, each with its own temperature control and device subgroup. This segmentation allows each sequence to maintain accurate temperature-specific testing while the overall system achieves high equipment utilization through parallel execution of multiple sequences without idle ramping time.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces overall testing time, minimizes robotic handling and potential damage to semiconductors, improves test data precision, and maximizes equipment utilization by eliminating or reducing index time, thereby enhancing the efficiency and return on investment in automated test equipment and handlers.

Implementation Method 1

ramping the first portion of the first subgroup from the first testing temperature to a second testing temperature

Methodology Applied
Scientific EffectTemperature ramping: Heating

Implementation Method 2

testing the first portion of the first subgroup at a first testing temperature, which is the ambient temperature

Methodology Applied
Scientific EffectTemperature testing: Thermography

Data Source

PatentUS10386405B2Method for continuous tester operation during multiple stage temperature testing
Publication Date: 2019.08.20 CELERINT LLC
  • US10386405B2 patent drawing
  • US10386405B2 patent drawing
  • US10386405B2 patent drawing

AI summary

A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.