Continuous Solder Tape for Fine Pitch Flip-Chip Interconnects
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Solution Overview
Problem
The existing methods for forming electrical interconnections between semiconductor dies and substrates are slow, costly, and wasteful, and do not allow for fine pitch interconnects due to the use of individual bump material deposition and reflow processes.
Innovation Solution
A method involving the formation of a continuous body of solder tape with recesses, deposition of flux material, and reflowing the solder tape under surface tension to create electrical interconnects within the footprint of the contact pads, eliminating the need for conventional bumping processes and enabling fine pitch connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual bump material deposition and reflow processes are used, then electrical interconnections can be formed, but the manufacturing process becomes slow, costly, and wasteful
Solution Approach 1:
The patent merges multiple individual bump deposition operations into a single continuous solder tape application process. The solder tape contains pre-formed bumps at specified pitch intervals, allowing simultaneous placement of multiple interconnections in one step, thereby dramatically increasing manufacturing productivity while maintaining connection quality
Solution Approach 2:
The bumps are pre-formed on the solder tape at the required pitch and position before the assembly process. This preliminary preparation eliminates the need for individual deposition operations during manufacturing, enabling faster production without sacrificing interconnection reliability
2Reliability
If individual bump material deposition is used, then electrical interconnections can be formed, but bump material is wasted
Solution Approach 1:
By combining multiple bumps into a continuous tape structure, the process eliminates the material waste associated with individual deposition operations. The solder tape delivers precisely the required amount of material for each bump position without excess, reducing material loss while ensuring reliable electrical connections
3Manufacturing precision
If conventional bumping processes are used, then electrical interconnections can be formed, but fine pitch interconnects are not enabled
Solution Approach 1:
The solder tape is segmented into discrete bumps at precise pitch intervals during its fabrication. This segmentation allows fine pitch interconnects to be achieved while maintaining manufacturing efficiency, as the pre-segmented tape can be applied continuously without requiring individual deposition operations for each fine-pitch connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and cost while allowing for efficient and precise electrical interconnects between semiconductor dies and substrates, providing greater standoff height and enabling smaller, more densely packed semiconductor devices.
Implementation Method 1
separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and contact pads of the substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads
Data Source
AI summary
A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and contact pads of the substrate. A solder tape formed as a continuous body of solder material with a plurality of recesses is disposed between the contact pads of the semiconductor die and substrate. The solder tape is brought to a liquidus state to separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads of the semiconductor die and substrate. The contact pads on the semiconductor die and substrate can be formed with an extension or recess to increase surface area of the contact pads.