Continuous Spacer Semiconductor Arrangement for Gate Isolation
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Solution Overview
Problem
Conventional semiconductor structures, particularly FinFETs, face issues with electrical shorts and reduced integration density due to gaps in Inter-Layer Dielectric (ILD) and misalignment between fin ends and gate edges, which are exacerbated by the miniaturization trend.
Innovation Solution
A semiconductor arrangement where spacers extend continuously across gate stacks and dummy gates, with dielectric isolation defined by mask overlays, allowing for reduced gap dimensions between gate stacks and improved alignment of fin ends with spacers, thereby preventing electrical shorts and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional discontinuous spacers are used on gate stacks and dummy gates, then manufacturing is simpler, but electrical shorts occur between contacts due to gaps in the Inter-Layer Dielectric
Solution Approach 1:
The patent merges the spacers on gate stacks and dummy gates into a single continuous spacer structure. This is achieved by forming spacers on sidewalls of both gate stacks and dummy gates simultaneously, such that the spacers extend continuously across the entire gate region without gaps. The continuous spacer prevents electrical shorts between contacts by eliminating gaps in the Inter-Layer Dielectric, thereby resolving the technical contradiction between reliability and device complexity.
2Manufacturing precision
If lithography is used to define gate stack intervals, then manufacturing is easier, but the interval between gate stacks cannot be reduced below Critical Dimension limits
Solution Approach 1:
The patent uses continuous spacers as an intermediary structure to define the interval between gate stacks. Instead of relying on lithography to directly pattern the gate stack spacing, the continuous spacer serves as a self-aligned reference structure that guides subsequent processing steps. This intermediary approach enables gate stack intervals to be defined with precision below lithography Critical Dimension limits while maintaining ease of manufacture through self-alignment mechanisms.
3Ease of manufacture
If dummy gates are used for patterning convenience, then manufacturing is easier, but gaps in ILD between dummy gates cause electrical shorts
Solution Approach 1:
The patent merges the spacers on dummy gates with the spacers on gate stacks into a continuous spacer structure. By forming spacers on sidewalls of dummy gates simultaneously with gate stacks, the patent eliminates gaps in the Inter-Layer Dielectric that would otherwise occur between dummy gates. This continuous spacer structure maintains the patterning convenience provided by dummy gates while preventing electrical shorts, thereby resolving the contradiction between ease of manufacture and reliability.
Data Source
AI summary
A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.