Continuous-Time Pipeline ADC Removing Sample-and-Hold Circuits
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face limitations in high-speed signal processing due to the need for multiple sample-and-hold circuits, which increase power consumption and circuitry space, especially as bandwidth requirements rise with higher frequency applications.
Innovation Solution
A continuous-time pipeline ADC design is implemented, where each converter stage generates coarse digital signals and a residue signal in continuous-time form, reducing the number of T/H circuits and improving wideband performance by connecting multiple stages in series with a clock signal and analog input, and using encoders, decoders, delaying converters, and amplifiers to process signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple T/H circuits are used in discrete-time pipeline structure, then signal processing capability is improved, but power consumption and circuitry space increase
Solution Approach 1:
The patent extracts and removes the T/H circuits from the pipeline ADC structure, transitioning from discrete-time to continuous-time operation. By eliminating these sampling circuits, the patent reduces power consumption and circuit complexity while maintaining signal processing capability through continuous-time filtering and processing stages.
Solution Approach 2:
The patent inverts the conventional approach by operating in continuous-time rather than discrete-time. Instead of sampling and holding signals in discrete intervals, the system processes signals continuously through the pipeline stages, fundamentally changing the time domain operation to reduce circuit requirements.
2Speed
If multiple T/H circuits and clock drivers are added, then conversion speed is improved, but circuitry space increases
Solution Approach 1:
The patent removes multiple T/H circuits and their associated clock drivers from the architecture. By eliminating these discrete-time sampling components, the patent reduces the circuitry space required while achieving high conversion speeds through continuous-time processing and oversampling techniques.
Solution Approach 2:
The patent inverts the conventional discrete-time approach by using continuous-time operation throughout the pipeline. This inversion eliminates the need for multiple clocked sampling circuits, reducing area while maintaining high-speed performance through continuous signal flow and digital filtering.
3Measurement precision
If sampling rate is increased to meet bandwidth requirements, then frequency response is improved, but T/H circuit settling time requirements increase
Solution Approach 1:
The patent inverts the conventional approach by operating in continuous-time rather than discrete-time. This eliminates the settling time constraint inherent in T/H circuits, as continuous-time filters can process high-frequency signals without requiring the sampling circuits to settle between conversions, thereby achieving wide bandwidth without settling time penalties.
Solution Approach 2:
By removing the T/H circuits entirely, the patent eliminates the settling time bottleneck. The continuous-time architecture allows the system to achieve high bandwidth and frequency response without the time constraints imposed by discrete-time sampling and holding operations.
Data Source
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AI summary
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.