Continuous-Time Sampler Circuit Using Delay-Line Tap Switching
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges with noise and non-linearities due to switched-capacitor circuits, particularly in wideband applications, where issues like aliasing and 'kT/C' noise are undesirable.
Innovation Solution
A continuous-time sampler using series-connected delay lines with intermediate output taps and controlled switches, which stores time-shifted waveforms of the input signal, allowing the same input value to be made available at the output without switched-capacitor circuits, thereby avoiding noise and non-linearities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switched-capacitor circuits are used in ADCs, then the conversion function is achieved, but noise and non-linearities are introduced
Solution Approach 1:
The patent extracts and removes the switched-capacitor circuits from the ADC architecture, replacing them with continuous-time sampling circuits. This extraction eliminates the source of kT/C noise and non-linearities while preserving the essential signal conversion function through alternative circuitry that operates in continuous time rather than discrete switched intervals.
Solution Approach 2:
The patent changes the fundamental operating parameter from discrete-time switching to continuous-time operation. By transitioning from switched-capacitor discrete sampling to continuous-time sampling with delay lines and buffers, the system alters the temporal characteristic of signal processing, thereby eliminating noise mechanisms inherent to switching operations while maintaining conversion accuracy.
2Productivity
If switched-capacitor circuits are used, then ADC conversion is enabled, but aliasing occurs in wideband applications
Solution Approach 1:
The patent implements continuous-time sampling that maintains uninterrupted signal processing throughout the conversion process. By using continuous delay lines and buffers instead of periodic switching, the system ensures continuous action without the gaps that cause aliasing, while preserving high conversion speed through efficient continuous-time architecture.
3Reliability
If delay lines with output taps and controlled switches are used, then time-shifted waveforms are stored, but device complexity increases
Solution Approach 1:
The patent designs delay lines with multiple output taps that serve multiple functions simultaneously: storing time-shifted waveforms, providing sampled values at different time points, and enabling continuous-time operation. This multi-functionality reduces the need for separate components, thereby managing complexity while achieving reliable signal storage and processing.
4Object-generated harmful factors
If continuous-time sampling is implemented, then noise and non-linearities are eliminated, but circuit design becomes more challenging
Solution Approach 1:
The patent segments the continuous-time sampling circuit into modular functional blocks: delay lines with specific tap positions, controlled switches with defined switching characteristics, and buffer amplifiers. This segmentation allows each component to be designed and optimized independently, simplifying the overall manufacturing process while maintaining the noise-reduction benefits of continuous-time operation.
Data Source
AI summary
A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.