Continuous-Time SAR ADC Architecture With Smaller Input Capacitors
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Solution Overview
Problem
Conventional successive approximation analog-to-digital converters (SAR ADCs) face challenges with high power consumption and large circuit area due to the use of large input capacitors required for stringent linearity, especially at high resolutions, which leads to significant sampling noise and increased size.
Innovation Solution
A two-step successive approximation register (SAR) ADC circuit operates in the continuous-time domain for the first stage without a front-end sampling circuit, using a floating inverter-based dynamic amplifier for low-pass filtering and redundancy to minimize conversion errors, allowing for a substantially smaller input capacitor size and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large input capacitor is used in conventional SAR ADC to meet linearity requirements, then measurement precision is improved, but power consumption and circuit area increase significantly
Solution Approach 1:
The ADC is divided into two stages: a first-stage continuous-time SAR ADC that operates without a front-end sampling circuit, and a second-stage discrete-time SAR ADC. This segmentation allows the first stage to use a much smaller input capacitor while maintaining linearity through continuous-time operation, thereby reducing power consumption and circuit area compared to conventional single-stage designs that require large capacitors for high-resolution conversion.
2Measurement precision
If a large input capacitor is used in conventional SAR ADC, then measurement precision is improved, but circuit area increases significantly
Solution Approach 1:
The ADC architecture is segmented into continuous-time and discrete-time stages, allowing the first stage to achieve high linearity with a small capacitor by operating continuously rather than through discrete sampling. This eliminates the need for large front-end sampling capacitors, significantly reducing the overall circuit area while maintaining measurement precision.
Solution Approach 2:
A floating inverter-based dynamic amplifier is introduced as an intermediary component between the first-stage residue output and the second-stage input. This amplifier provides low-pass filtering that reduces sampling noise and maintains signal integrity, enabling the system to use smaller capacitors without compromising linearity or increasing circuit area.
3Ease of operation
If a front-end sampling circuit is used in conventional SAR ADC, then input signal acquisition is achieved, but sampling noise increases and capacitor size must be large
Solution Approach 1:
The front-end sampling circuit is extracted and removed from the first-stage continuous-time SAR ADC. Instead of using discrete sampling that introduces significant noise and requires large capacitors, the system directly processes the continuous-time input signal through the first-stage SAR converter, thereby eliminating sampling noise at the input stage while maintaining effective signal acquisition.
Solution Approach 2:
The floating inverter-based dynamic amplifier acts as an intermediary that filters out sampling noise from the second stage while preserving the benefits of continuous-time operation in the first stage. This low-pass filtering intermediary allows the system to achieve clean signal acquisition without the harmful effects of front-end sampling noise.
4Ease of operation
If conventional Nyquist ADC with front-end sample-and-hold circuit is used, then input signal sampling is achieved, but input capacitor size must be at least 20 times larger
Solution Approach 1:
The ADC is segmented into two functional stages with different sampling approaches: the first stage operates in continuous-time without front-end sampling, using a small capacitor, while the second stage performs discrete-time sampling. This segmentation allows the system to achieve effective input signal sampling without requiring the large input capacitor (at least 20 times smaller than conventional designs) that would be needed for high-resolution Nyquist-rate sampling in a single stage.
Data Source
AI summary
The exemplified disclosure presents a successive approximation register analog-to-digital converter circuit that comprises a two-step (e.g., two-stage) analog-to-digital converter (ADC) that operates a 1st-stage successive approximation register (SAR) in the continuous time (CT) domain (also referred to as a “1-st stage CTSAR”) that then feeds a sampling operation location in the second stage. Without a front-end sampling circuit in the 1st-stage, the exemplary successive approximation analog-to-digital converter circuit can avoid high sampling noise associated with such sampling operation and thus can be configured with a substantially smaller input capacitor size (e.g., at least 20 times smaller) as compared to conventional Nyquist ADC with a front-end sample-and-hold circuit.