Continuous Via Conductive Structure for Semiconductor Memory Alignment
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing size and improving operation reliability due to alignment shifts and increased electrical resistance caused by separate formation of vias and conductive layers.
Innovation Solution
The integration of vias and conductive layers into a single continuous layer reduces alignment shifts and electrical resistance, enhancing alignment accuracy and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vias and conductive layers are formed separately, then manufacturing process flexibility is improved, but alignment accuracy deteriorates and electrical resistance increases
Solution Approach 1:
The patent merges the via formation and conductive layer formation into a single integrated process step. The conductive layer is formed to simultaneously fill the via region and extend onto the pad region, creating a continuous conductive structure that eliminates alignment shifts between separate via and conductive layer formations.
2Device complexity
If vias and conductive layers are formed separately, then process complexity is reduced, but electrical resistance increases due to contact area reduction
Solution Approach 1:
The conductive layer is designed as a continuous structure that merges the via fill function with the pad connection function. This integration ensures maximum contact area between the via and pad regions, minimizing electrical resistance while maintaining a relatively simple single-step formation process.
Solution Approach 2:
The conductive layer extends in multiple dimensions, transitioning from a simple via fill to a three-dimensional structure that covers both the via region and pad region. This dimensional extension increases the contact area and reduces electrical resistance at the interface.
3Volume of moving object
If device size is reduced, then integration density is improved, but alignment errors have greater impact on reliability
Solution Approach 1:
The integrated conductive structure eliminates the need for separate via and conductive layer alignment, removing the primary source of alignment errors. This allows device miniaturization without proportionally increasing alignment error impact, as the merged structure maintains reliability even at smaller dimensions.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.