Continuous Via-Holes in Stacked Nonvolatile Memory
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Solution Overview
Problem
The existing multilayer-structured nonvolatile semiconductor devices require complex and costly processes for forming via-holes to connect word and bit lines in each layer, leading to increased manufacturing costs and complexity.
Innovation Solution
A nonvolatile semiconductor memory device with a cell array block comprising stacked layers connected by via-holes that are formed continuously through multiple layers, allowing for reduced processing steps and efficient connection of lines to the semiconductor substrate, with multiple via-holes having equal beginning and terminating positions connected to different lines in various layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via-holes are formed layer by layer to connect word and bit lines in each layer, then connection reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of multiple via-holes into a single continuous structure that penetrates through multiple cell array layers simultaneously. Instead of forming via-holes layer by layer, the invention creates one continuous via-hole structure that connects word lines and bit lines across different layers, reducing the number of formation steps while maintaining reliable electrical connections.
Solution Approach 2:
The continuous via-hole structure serves multiple functions simultaneously: it connects word lines across different cell array layers, connects bit lines across different layers, and provides electrical pathways through multiple insulating layers. This multi-functional design eliminates the need for separate via-hole formation processes for each connection.
2Manufacturing precision
If via-holes are formed layer by layer to connect word and bit lines in each layer, then connection precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple via-hole formation operations into a single continuous via-hole structure formed in one manufacturing process. This merging approach maintains precise alignment of via-holes with word lines and bit lines across multiple layers while significantly reducing the number of separate formation steps required, thereby lowering manufacturing costs.
3Reliability
If multiple via-hole formation steps are used to connect lines in stacked layers, then connection reliability is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary planning of the continuous via-hole structure to ensure it can accommodate all necessary connections across multiple cell array layers. By designing the via-hole formation process to create continuous structures that penetrate through multiple layers in advance, the invention eliminates the need for subsequent additional formation steps, reducing total processing time while maintaining reliable connections.
Data Source
AI summary
A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.