Contoured Gate Capping Dielectric for MTP Retention

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Retention failures in multi-time-programmable (MTP) devices occur due to thinning of the dielectric layer in the corner region around the gate electrode, affecting device performance and reliability.

Innovation Solution

A contoured gate capping dielectric is used to protect the gate electrode during processing steps, enhancing retention characteristics by covering the top corner portions of the gate electrode, thereby improving multiple-time-programming retention without modifying structures for logic-side field effect transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional gate electrode structure is used without additional protection, then the device structure remains simple, but the dielectric layer thins in the corner region around the gate electrode causing retention failures

Engineering Contradiction:

Improveretention characteristicsVSAvoidgate electrode structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A contoured gate capping dielectric is formed over the gate electrode before subsequent processing steps. This preliminary protective structure prevents dielectric layer thinning in the corner regions during later manufacturing processes, thereby improving retention characteristics without requiring modifications to the logic-side field effect transistors.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The contoured gate capping dielectric provides localized protection specifically at the corner regions around the gate electrode where dielectric thinning occurs. This targeted approach addresses the specific problem area without unnecessarily complicating the entire device structure, maintaining simplicity in non-affected regions.

Inventive Principle:

Principle #3Local quality

2Volume of moving object

If the dielectric layer is made thinner to reduce device size, then the device dimensions are reduced, but retention failures occur due to dielectric layer thinning in corner regions

Engineering Contradiction:

Improvedevice dimensionsVSAvoidretention characteristics

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The contoured gate capping dielectric is formed in advance to protect the gate electrode structure. This preliminary protection enables the use of thinner dielectric layers in the overall device design while preventing the specific thinning problem in corner regions that would cause retention failures, thus allowing size reduction without sacrificing reliability.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20240381637A1Field effect transistor with top-protected gate electrode and methods for forming the same

Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.