Contoured Semiconductor Surfaces for Improved Adhesion
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Solution Overview
Problem
In integrated circuit fabrication, particularly for memory devices, accessing semiconductor surfaces is challenging due to adjacent structures like digit lines, which limit access and result in poor overlap and adhesion of features with these surfaces, especially as integration levels increase.
Innovation Solution
A method involving selective etching techniques, including a hybrid etching process using silicon, wet hydrofluoric-acid, and vapor etches with ammonia, to contour the upper surfaces of semiconductor regions, creating a flat-topped peak and concavity configuration that improves contact and adhesion with subsequent semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional fabrication methods are used to form features over semiconductor surfaces, then manufacturing process simplicity is maintained, but access to semiconductor surfaces is limited and adhesion is poor due to adjacent structures like digit lines
Solution Approach 1:
The patent applies preliminary action by performing etching operations to contour the semiconductor surface before depositing the conductive pillar. This pre-shaping of the surface creates better geometric alignment and contact area between the pillar and semiconductor region, improving access and adhesion before the actual feature formation occurs.
Solution Approach 2:
The patent replaces mechanical contact-based alignment with etching-based geometric conforming. Instead of relying on mechanical positioning of features over surfaces, the method uses selective etching to create a contoured surface geometry that naturally guides and improves the contact between subsequent deposited materials and the semiconductor region.
2Reliability
If features are formed directly over semiconductor surfaces without surface modification, then fabrication steps are reduced, but overlap and adhesion between features and surfaces are poor
Solution Approach 1:
The etching step is performed as a preliminary action before feature deposition. This pre-treatment of the semiconductor surface creates a contoured geometry with increased surface area and improved geometric matching, which directly enhances adhesion and overlap quality when conductive pillars or other features are subsequently formed.
Solution Approach 2:
The patent changes the geometric parameters of the semiconductor surface through selective etching. By modifying the surface topology to create peaks and valleys, the method alters the physical contact parameters between the semiconductor and subsequent features, improving adhesion through increased contact area and better geometric alignment.
3Productivity
If integration levels are increased to improve device density, then productivity is improved, but access to semiconductor surfaces becomes increasingly difficult and adhesion deteriorates
Solution Approach 1:
The patent applies local quality by performing selective etching only in specific regions where features need to be formed. The etching process targets particular semiconductor regions adjacent to digit lines and other structures, creating localized contoured surfaces only where needed for feature formation, while leaving other areas unchanged for continued high-density integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively exposes and modifies semiconductor surfaces, enhancing the quality of electrical contacts and adhesion, thereby overcoming access and adhesion issues in high-integration memory devices.
Implementation Method 1
modifying a upper surface of the exposed semiconductor material region to form a contoured surface. The contoured surface includes a flat-topped peak and a concavity
Data Source
AI summary
Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.