Control Chip Memory Partitioning for Faster Sensor Data Access

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Solution Overview

Problem

Computer memory systems face inefficiencies when frequently reading data between different specified addresses, leading to prolonged data output times.

Innovation Solution

A control chip with a first and second memory area and a processing circuit, where the accessing circuit reads continuous data from the first area and processing parameters from the second area to generate read data, which is then processed and stored in the second memory, optimizing data access and processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the memory frequently reads data between different specified addresses, then the memory can access different data, but the data output time becomes long

Engineering Contradiction:

Improvedata access flexibilityVSAvoiddata output time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The memory is divided into two distinct storage areas: a first storage area for storing continuous sensing data and a second storage area for storing processing parameters. This segmentation allows the accessing circuit to read continuous data from the first storage area using a single start address, eliminating the need to repeatedly specify different addresses for different data segments, thereby reducing data output time while maintaining access flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first storage area is pre-configured to store continuous sensing data in a sequential manner, and the second storage area is pre-configured to store processing parameters. This preliminary organization of data allows the accessing circuit to perform bulk reading operations with minimal address specifications, reducing the time required for data output while preserving the ability to access different data types.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the accessing circuit reads continuous data from the first storage area, then the data reading efficiency improves, but the device complexity increases

Engineering Contradiction:

Improvedata reading efficiencyVSAvoidmemory structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory device is designed with multi-functionality by incorporating both a first storage area for sensing data and a second storage area for processing parameters within the same memory structure. This universal design allows the memory to handle both continuous data reading and parameter access operations, improving data reading efficiency without requiring separate memory devices, thus controlling device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If the processing circuit processes data simultaneously with storage operations, then the overall processing efficiency enhances, but the device complexity increases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidcircuit structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The processing circuit and memory accessing operations are merged into a coordinated system where the accessing circuit reads continuous data from the first storage area and simultaneously the processing circuit processes this data while results are stored in the second storage area. This integration allows simultaneous processing and storage operations, enhancing overall processing efficiency while managing circuit complexity through unified control.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The system maintains continuous useful action by enabling the processing circuit to process data as it is being read from the first storage area, with results being simultaneously stored in the second storage area. This continuous operation eliminates idle time between reading and processing, enhancing processing efficiency while the coordinated control manages circuit complexity.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12547347B2Control chip and evaluation board

Publication Date: 2026.02.10 NUVOTON

AI summary

A control chip coupled to a sensing circuit and including a first memory, an accessing circuit, a second memory, and a processing circuit is provided. The first memory includes a first storage area and a second storage area. The first storage area stores sensing data provided by the sensing circuit. The second storage area stores processing parameters. The accessing circuit reads continuous data of the first storage area according to a first access command to generate first read data and reads at least one processing parameter of the second storage area according to a second access command to generate second read data. The second memory stores the first and second read data. The processing circuit reads the second memory and processes the first read data according to the second read data to generate first processed data. The processing circuit stores the first processed data in the second memory.