Control Circuit Arrangement Verification for Semiconductor Floor Plans
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Solution Overview
Problem
Conventional methods for verifying the arrangement of control circuits in semiconductor devices require generating a net list and manually inserting control circuits, leading to lengthy failure/no-failure tests and limiting the ability to test multiple circuit arrangements due to time constraints.
Innovation Solution
An arrangement verification apparatus that includes a floor plan generation unit, a grouping generation unit to create a group tree, and a control circuit arrangement unit to arrange control circuits based on circuit specifications, allowing for a failure/no-failure test without the need for a net list, thereby reducing testing time and enabling the examination of multiple arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional net list generation and manual control circuit insertion methods are used, then the arrangement verification can be performed, but the testing time becomes excessively long (several days to several weeks)
Solution Approach 1:
The invention extracts and eliminates the unnecessary net list generation step from the conventional verification process. By directly inputting circuit specifications without requiring net list conversion, the method removes a time-consuming intermediate processing stage while maintaining verification accuracy.
Solution Approach 2:
The invention performs preliminary arrangement verification by automatically arranging control circuits based on circuit specifications before final design completion. This allows verification to occur earlier in the design process, significantly reducing the overall testing time while ensuring arrangement correctness.
2Adaptability or versatility
If multiple types of circuitry arrangements are to be tested in the development phase, then design quality can be enhanced, but the time pressure from lengthy testing prevents attempting multiple arrangements
Solution Approach 1:
The invention enables dynamic testing of multiple circuit arrangements by allowing rapid re-arrangement and re-verification of control circuits. The automated arrangement system can quickly generate different configuration options based on the same circuit specifications, enabling designers to evaluate multiple arrangements within the development phase time constraints.
Solution Approach 2:
The invention changes the verification approach from manual net list-based processing to automated specification-based processing. This parameter change in the verification method dramatically reduces testing time, enabling the evaluation of multiple circuit arrangements during the development phase rather than being limited to a single arrangement.
3Manufacturing precision
If manual control circuit insertion and net list generation are used, then the verification process follows conventional standards, but design rework increases and multiple arrangements cannot be efficiently examined
Solution Approach 1:
The invention replaces the manual mechanical process of net list generation and control circuit insertion with an automated computational system. The arrangement verification apparatus automatically processes circuit specifications and arranges control circuits without manual intervention, reducing process complexity while maintaining verification accuracy.
Data Source
AI summary
An arrangement verification apparatus that makes it possible to shorten a time it takes to complete a failure/no-failure test on the arrangement of control circuits that control block circuits is provided. The arrangement verification apparatus arranges block circuits to be controlled comprising a semiconductor device and control circuits that control the block circuits over a predetermined floor and conducts a failure/no-failure test on the arrangement of the control circuits. The arrangement verification apparatus includes: a floor plan generation unit that arranges block circuits over a floor based on circuit specifications; a grouping generation unit that hierarchically groups the block circuits arranged over the floor and control circuits described in the circuit specifications based on a predetermined requirement to generate a group tree; a control circuit arrangement unit that arranges the control circuits over the floor according to a predetermined condition and the group tree generated at the grouping generation unit; and a failure/no-failure test unit that conducts a failure/no-failure test on the arrangement of the control circuits by the control circuit arrangement unit.