Control Device Authentication Chain for Lower Host Load
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Solution Overview
Problem
Existing authentication methods for multiple chips in host devices require multiple interactions between the host device and each chip, leading to a high load on the host device as the number of chips increases.
Innovation Solution
A method and device that acquire first authentication data on a communication bus and obtain second authentication data to determine if any chip does not meet expectations, reducing interactions by only requiring communication with the first and last chips, thereby lowering the host device's load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host device authenticates each chip separately by exchanging information multiple times, then authentication security is improved, but the load on the host device increases
Solution Approach 1:
The patent merges the authentication process by having chips perform sequential authentication where each chip (except the last) passes authentication data to the next chip, which continues the authentication sequence. This combines multiple individual authentication interactions into a single chain process, reducing the host device's interaction burden while maintaining security through the cumulative authentication data collected across all chips.
2Reliability
If the host device interacts with each chip multiple times for authentication, then authentication thoroughness is improved, but the number of communication transactions increases
Solution Approach 1:
The patent introduces intermediary chips that relay authentication data between the host device and subsequent chips in the chain. Each chip acts as an intermediary, receiving authentication data from the previous chip and passing processed authentication data to the next chip. This intermediary mechanism allows thorough authentication to be performed across multiple chips while reducing the number of direct communication transactions required from the host device.
3Measurement precision
If separate authentication is performed for each chip, then individual chip verification is improved, but system performance overhead increases
Solution Approach 1:
The patent segments the authentication process into discrete steps where each chip performs authentication independently on received data and generates authentication results that are passed to the next chip. This segmentation allows individual chip verification to be maintained through each chip's independent authentication logic, while the overall system performance is improved by eliminating redundant host device interventions and creating a streamlined sequential process.
Data Source
AI summary
The present disclosure provides a control device, consumables, a host device, and an authentication method, where the control device includes a first acquisition unit, where the first acquisition unit is configured to acquire first authentication data on a communication bus, and the communication bus is configured for communication linkage between the host device and at least two chips; an authentication unit, which obtains second authentication data based on the first authentication data, where the second authentication data is used to determine total authentication data, and the total authentication data is used to determine whether there is a chip, of the at least two chips, that does not meet expectations.