Control Device Dual-Buffer Architecture for Memory Access Time
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Solution Overview
Problem
Existing control devices for accessing between volatile and non-volatile memories face inefficiencies due to sequential execution of instruction sets, leading to longer access times as they wait for processing units to write new instruction sets before execution.
Innovation Solution
A control device with an execution unit, storage units, a selection unit, and a processing unit that executes specific instruction sets to access memories, where the selection unit outputs instruction sets based on control signals generated by the processing unit, allowing simultaneous execution and writing of multiple instruction sets without waiting for processing completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the execution unit waits for the processing unit to write new instruction sets before execution, then the system ensures proper sequencing and control, but the access time increases due to sequential execution
Solution Approach 1:
The patent implements a dual-buffer architecture where the processing unit writes instruction sets to a buffer in advance. The execution unit can then execute from this pre-prepared buffer without waiting for the processing unit to complete writing, thereby overlapping the write and execute operations and reducing access time.
Solution Approach 2:
The patent divides the instruction storage into multiple segments or buffers (first buffer and second buffer). This segmentation allows the execution unit to access one buffer while the processing unit writes to another, enabling parallel operations and eliminating the sequential wait time that would occur with a single buffer.
2Device complexity
If the system uses a single instruction set buffer, then the device complexity is reduced, but the execution unit must wait for processing completion leading to longer access times
Solution Approach 1:
The patent segments the instruction buffer into multiple independent buffers (first and second buffers). This segmentation increases the device complexity slightly but eliminates execution wait time by allowing the execution unit to access one buffer while the processing unit writes to another, thus trading minimal complexity for significant time savings.
3Device complexity
If the execution unit executes instruction sets sequentially one at a time, then the control logic is simplified, but the overall data transfer efficiency decreases
Solution Approach 1:
The processing unit prepares instruction sets in advance by writing them to the buffer before the execution unit needs them. This preliminary action allows the execution unit to execute instructions without waiting, improving data transfer efficiency while maintaining relatively simple control logic through the use of control signals that manage the buffer switching.
Data Source
AI summary
A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit.