Control Die Address Translation in Integrated Memory Assembly
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Solution Overview
Problem
The performance of memory systems using non-volatile memory is hindered by the time required for address translation, particularly when the L2P table needed for translation is not stored in the L2P cache, leading to cache misses and increased latency in fetching and transferring the table between non-volatile memory and the memory controller.
Innovation Solution
Implementing an integrated memory assembly with a control die that performs address translation directly on the memory die, eliminating the need to transfer the L2P table to the memory controller, thereby reducing latency and power consumption by allowing address translation to occur at the memory die level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the L2P table is stored in local volatile memory (L2P cache), then address translation speed is improved, but memory system cost and local memory size requirements increase
Solution Approach 1:
The patent moves the L2P table storage from local volatile memory to non-volatile memory, changing the storage dimension from fast but expensive local storage to slower but cheaper remote storage. This is compensated by implementing a cache-coherent architecture where the memory controller maintains cache coherence without requiring the L2P table to be physically present in local memory, thus resolving the contradiction between speed and memory size requirements.
2Ease of operation
If the L2P table is fetched from non-volatile memory to the memory controller during address translation, then address translation can be performed, but system latency increases due to fetch and transfer time
Solution Approach 1:
The patent implements preliminary actions by pre-fetching L2P tables into the memory controller's buffer before they are needed for address translation. The cache coherence mechanism proactively manages L2P table availability, ensuring that when address translation is needed, the L2P table is already in the buffer or being fetched in parallel with other operations, thus reducing the perceived latency.
Solution Approach 2:
The patent ensures continuous useful action by implementing an asynchronous L2P table fetch mechanism that operates in parallel with memory operations. The cache coherence protocol maintains continuous monitoring and management of L2P table validity, allowing address translation to proceed without interruption once the L2P table is available, thus minimizing latency while maintaining continuous system operation.
3Productivity
If a large L2P cache is implemented to store all L2P tables, then address translation performance is improved, but memory system cost increases
Solution Approach 1:
The patent makes the non-volatile memory serve multiple functions: it acts as both the primary data storage medium and the L2P table storage medium. The memory controller's buffer serves dual purposes as both data buffer and L2P table cache. This multi-functionality eliminates the need for separate large L2P cache memory, reducing overall system cost while maintaining address translation performance through intelligent buffer management and cache coherence protocols.
Data Source
AI summary
A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.