Composite Control Gate Dielectric for Dense Reliable Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional silicon-dioxide gate dielectrics in memory devices become unreliable and limit device performance as feature sizes decrease, leading to excessive charge leakage and reduced drive capability.
Innovation Solution
Incorporating a high-k dielectric material in the gate dielectric structure, which allows for thinner dielectric layers while maintaining or improving drive capability and reliability, enabling smaller-scale transistor implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of conventional silicon-dioxide gate dielectric is reduced to increase memory cell density, then memory cell density is improved, but device reliability deteriorates due to excessive charge leakage
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric material from conventional silicon-dioxide (k≈3.9) to high-k dielectric materials (k>7.0). This parameter change allows the dielectric layer to maintain lower equivalent oxide thickness (EOT) while preserving higher physical thickness, thereby achieving both high memory cell density and acceptable reliability by reducing charge leakage through the tunneling barrier.
Solution Approach 2:
The patent employs composite gate dielectric structures that combine high-k dielectric materials with other materials such as silicon nitride or silicon oxide layers. This composite approach allows optimization of both the dielectric constant and the tunneling barrier properties, enabling simultaneous achievement of high memory cell density through reduced EOT and improved reliability through suppressed charge leakage.
2Power
If the thickness of conventional silicon-dioxide gate dielectric is reduced, then drive capability is improved, but reliability worsens due to excessive charge leakage
Solution Approach 1:
By changing the dielectric constant parameter to high-k values, the patent achieves lower equivalent oxide thickness which enhances the electric field and improves drive capability, while the higher physical thickness of the high-k layer maintains a robust tunneling barrier that suppresses charge leakage and preserves reliability.
Solution Approach 2:
The composite gate dielectric structure combines high-k dielectric materials with additional layers that provide optimized tunneling barriers. This allows the structure to deliver high drive capability through reduced EOT while maintaining reliability through the combined effect of high-k material and barrier layers that suppress charge leakage.
3Quantity of substance
If feature size is reduced to increase memory cell density, then memory cell density is improved, but drive capability worsens due to thinner gate dielectric
Solution Approach 1:
The patent changes the dielectric constant parameter to high-k values, which allows the gate dielectric to achieve lower equivalent oxide thickness proportionate to the scaled feature size. This maintains the electric field strength and drive capability even as feature dimensions are reduced to increase memory cell density.
Solution Approach 2:
The composite gate dielectric structure enables proportional scaling of the tunneling barrier with feature size while maintaining drive capability. The high-k material allows the physical thickness to scale down with feature size for higher density, while the equivalent oxide thickness scales appropriately to preserve drive capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high-k dielectric material enhances the drive capability of access transistors and suppresses charge leakage, thereby improving the reliability and longevity of memory devices by overcoming the thickness limitations of conventional silicon-dioxide gate dielectrics.
Implementation Method 1
The gate dielectric structure can include different dielectric materials including a high-k dielectric material
Implementation Method 2
The control gate has a gate dielectric (often called gate oxide) to electrically isolate the control gate from adjacent structures of the memory cell
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a recess formed in a semiconductor material; a dielectric structure formed in the recess; and a control gate for a transistor of a memory cell, the control gate including a first conductive portion formed in the recess and separated from the semiconductor material by a first portion of the dielectric structure, the first dielectric portion including a first dielectric material between the semiconductor material and the second dielectric material, and a second dielectric material between the first dielectric material and the first conductive portion; and the control gate including the second conductive portion formed over the first conductive portion and separated from the semiconductor material by a second portion of the dielectric structure between the semiconductor material and second conductive portion.