Control Gate Height Adjustment for MONOS Reliability

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Solution Overview

Problem

In semiconductor devices with split-gate type MONOS memory cells, the formation of a silicide layer on the gate electrodes can lead to a short-circuit between the silicide layers, compromising the breakdown voltage and reliability of the device.

Innovation Solution

The height of the control gate electrode is made lower than the highest position of the silicide layer on the memory gate electrode, ensuring that the control gate electrode is not adjacent to the silicide layer via the ONO film, thus preventing short-circuits and maintaining the breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a silicide layer is formed on the gate electrode to reduce resistance, then electrical conductivity is improved, but the breakdown voltage decreases and short-circuit risk increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoidshort-circuit risk
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate electrode structure is segmented into two distinct parts: the control gate electrode and the memory gate electrode, separated by the ONO film. The silicide layer is selectively formed only on the memory gate electrode, while the control gate electrode remains free of silicide. This segmentation allows the silicide to provide low resistance where needed while preventing short-circuit risks at the control gate, thereby resolving the contradiction between conductivity improvement and breakdown voltage maintenance.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the control gate electrode height is reduced to prevent contact with silicide layer, then breakdown voltage is maintained, but manufacturing precision requirements increase

Engineering Contradiction:
Improvebreakdown voltageVSAvoidelectrode height control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The control gate electrode height is predetermined and controlled during the formation process to be lower than the memory gate electrode height by a specific margin (5 nm to 50 nm). This preliminary height differentiation is established before silicide layer formation, ensuring that even with normal manufacturing variations, the control gate electrode will not contact the silicide layer on the memory gate electrode, thus maintaining breakdown voltage while accounting for manufacturing tolerances.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12302610B2Semiconductor device
Publication Date: 2025.05.13 RENESAS ELECTRONICS CORP
  • US12302610B2 patent drawing
  • US12302610B2 patent drawing
  • US12302610B2 patent drawing

AI summary

A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.