Control Gate Impurity Profile for Low-Voltage NVM Erase
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Solution Overview
Problem
Existing semiconductor Non-Volatile Memory (NVM) devices require strong electrical fields for efficient erasing, which necessitates high voltage biases and prolonged application times, limiting endurance and efficiency.
Innovation Solution
The design of a lateral impurity profile for the control gate with low concentrations in the middle region and high concentrations at the edges, reducing control gate-to-floating gate capacitance and optimizing electrical field distribution to enhance erasing efficiency while minimizing voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If strong electrical fields are applied to enable efficient erasing, then erasing efficiency is improved, but voltage bias requirements and application time increase
Solution Approach 1:
The control gate is designed with non-uniform impurity distribution, featuring high impurity concentration at the edges and low impurity concentration in the middle region. This creates localized depletion regions at the edges that concentrate electrical field strength at the dielectric interfaces, enabling efficient Fowler-Nordheim tunneling without requiring uniformly high voltage across the entire control gate structure.
Solution Approach 2:
The patent modifies the impurity concentration parameters within the control gate material to create a specific lateral profile. By changing the impurity concentration distribution from uniform to non-uniform (high at edges, low in middle), the electrical field distribution is optimized to achieve strong fields at the tunneling interfaces while reducing overall voltage requirements.
2Productivity
If strong electrical fields are applied to enable efficient erasing, then erasing efficiency is improved, but application time increases
Solution Approach 1:
The localized high impurity concentration regions at the control gate edges create concentrated depletion regions that generate intense electrical fields precisely where needed at the dielectric interfaces. This localized field concentration enables rapid Fowler-Nordheim tunneling of electrons, reducing the time required for complete erasure while maintaining high efficiency.
Solution Approach 2:
The patent employs pulsed voltage biasing schemes where high voltage is applied in periodic pulses to the control gate. The non-uniform impurity profile ensures that during each pulse, the strongest fields are generated at the edge regions, enabling efficient charge removal in discrete time intervals that reduce overall application time compared to continuous low-field erasing.
3Power
If control gate-to-floating gate capacitance is reduced, then voltage difference is maximized, but electrical field distribution must be optimized
Solution Approach 1:
The control gate features a specific lateral impurity profile with high concentration at edges and low concentration in the middle. This non-uniform distribution creates edge-depletion regions that reduce the control gate-to-floating gate capacitance while concentrating the electrical field at the dielectric interfaces, thereby maximizing voltage difference across the tunneling barrier without requiring complex external circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient tunneling erase operations with reduced voltage biases and shorter application times, improving the endurance and efficiency of NVM devices by maximizing voltage differences across the floating and control gates.
Implementation Method 1
the capacitive coupling between the charge storage material and control gate can be designed to generate a strong electrical field
Implementation Method 2
Fowler-Nordheim tunneling current in oxides (dielectrics) is given by... significant amounts of stored electrons in the floating gate 105 can be then tunneled out
Implementation Method 3
a charge depletion region 201d of the control gate 201 is formed from the dielectric interface 201c into the control gate electrode 201a caused by the low impurity concentrations
Data Source
AI summary
For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.