Control Gate Pad Layout for Split-Gate Flash Word Line Etching
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Solution Overview
Problem
The challenge in forming word lines for split-gate flash memory cells is the small spacing between control gates, which leads to hard mask merging, decreased etch process window, and non-uniform widths, resulting in reduced manufacturing yield and potential device failure.
Innovation Solution
The solution involves a control gate layout where pad regions protrude towards both the erase gate and word line, increasing the spacing between control gates, preventing hard mask merging, and ensuring uniform etch process windows, thereby enhancing manufacturing yield and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control gates are placed close together to increase memory density, then storage capacity is improved, but hard mask merging occurs during word line etching
Solution Approach 1:
The control gate is segmented into multiple sections with pad regions protruding towards both the erase gate and word line. This segmentation creates distinct zones that prevent hard mask merging during etching while maintaining close spacing for high density. The pad regions act as isolated segments that preserve etch process integrity.
Solution Approach 2:
Different regions of the control gate are given different geometrical properties. The pad regions have protruding structures that locally modify the spacing characteristics, creating areas of increased spacing specifically where etching occurs, while other regions maintain tight spacing for density. This local geometrical modification prevents hard mask merging without sacrificing overall memory density.
2Quantity of substance
If control gate spacing is reduced to increase density, then storage capacity is improved, but etch process window decreases
Solution Approach 1:
The control gate structure is divided into functional segments with pad regions that protrude towards adjacent structures. This segmentation creates localized spacing variations that preserve adequate etch process windows in critical areas while allowing reduced spacing in non-critical areas to achieve high density.
Solution Approach 2:
The pad regions introduce a geometrical dimensionality change by protruding in specific directions towards the erase gate and word line. This dimensional modification creates additional spacing in the etch direction without increasing overall footprint, thereby maintaining etch process window while achieving high density through optimized spatial arrangement.
3Manufacturing precision
If control gate spacing is increased to prevent hard mask merging, then manufacturing yield is improved, but memory density decreases
Solution Approach 1:
Increased spacing is applied locally only at the pad regions where it is needed to prevent hard mask merging and ensure manufacturing yield. The rest of the control gate structure maintains tight spacing to preserve memory density. This selective application of spacing optimization achieves both manufacturing yield and high density.
Solution Approach 2:
The control gate is segmented into pad regions and non-pad regions with different spacing characteristics. The pad regions have increased spacing to prevent hard mask merging and improve manufacturing yield, while the non-pad regions maintain reduced spacing for high density. This segmentation allows simultaneous optimization of both manufacturing yield and memory density.
Data Source
AI summary
Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.