Control Gate Recess Profile Shaping for Straight Etch Sidewalls
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Solution Overview
Problem
Conventional semiconductor processing methods struggle to form control gate recesses with a substantially straight profile due to uneven etching, resulting in concave recessed surfaces that limit further size reductions in devices like 3D-NAND memory devices.
Innovation Solution
The method involves forming a semiconductor layer with different etch rates in various portions, counteracting the tendency of dry etching to etch the middle faster than the ends by increasing etch resistance in the middle, achieved through gradients in dopant atomic percentage and stress levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional uniform semiconductor layers are etched, then the etching process is simple and fast, but the recessed surface becomes concave due to faster etching in the middle compared to the ends
Solution Approach 1:
The semiconductor layer is engineered with spatially varying etch resistance properties. The middle portion of the layer has higher etch resistance than the end portions, creating a non-uniform etch resistance profile that compensates for the natural tendency of dry etching to etch the middle faster. This local differentiation of material properties enables straight recessed surfaces while maintaining a relatively simple layered structure.
Solution Approach 2:
The etch resistance parameter of the semiconductor layer is modified by changing the dopant concentration profile. By increasing the dopant atomic percentage in the middle portion of the layer compared to the ends, the etch resistance is locally enhanced. This parameter change transforms the uniform layer into one with controlled non-uniform etching characteristics, achieving straight profiles without complex multi-layer structures.
2Manufacturing precision
If the middle of the semiconductor layer has increased etch resistance, then the recessed surface profile becomes straighter, but the layer requires complex dopant gradients and stress control
Solution Approach 1:
The dopant gradient and stress profile are established during the initial deposition of the semiconductor layer, before any etching operations. By incorporating the etch resistance modulation into the layer formation process itself, the patent avoids the need for subsequent complex processing steps. The preliminary structuring of the layer with spatially varying properties enables the straight profile to be achieved during a single etching operation.
Solution Approach 2:
The deposition parameters are dynamically adjusted during layer formation to create the desired dopant concentration profile. By varying the dopant atomic percentage as a function of position in the layer (higher in the middle, lower at the ends), the etch resistance is controlled. This parameter modulation during deposition integrates the profile control into the manufacturing process, reducing the need for separate complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a substantially straight recessed surface with minimal concavity, enabling more precise control gate profiles and reducing critical dimensions in semiconductor devices.
Implementation Method 1
the semiconductor layer may be formed with increased etch resistance in the middle of the layer compared to the ends of the layer
Data Source
AI summary
Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.