Flash Memory Control Gate Straps for Contact Landing and Interconnects
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Solution Overview
Problem
Existing flash memory cell arrays lack improved structures that facilitate efficient contact formation and interconnects for control gates, leading to potential manufacturing challenges and reduced performance.
Innovation Solution
The introduction of asymmetrical gate strap regions with projections on control gates in the flash memory cell array, allowing for enhanced landing of control gate contacts and efficient removal of select and erase gates, thereby facilitating better interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If asymmetrical gate strap regions with projections are introduced on control gates, then contact formation and interconnect efficiency are improved, but device structure complexity increases
Solution Approach 1:
The patent applies asymmetry by introducing gate strap regions with projections on only one sidewall of the control gate (first sidewall) while leaving the opposite sidewall without such projections. This asymmetric configuration enables directional contact formation and selective removal of select and erase gates, improving manufacturing efficiency without requiring symmetric modifications to both sides of the structure.
Solution Approach 2:
The gate strap region is segmented into distinct functional zones: a projection region extending outwardly from the first sidewall for contact formation, and a non-projection region on the second sidewall. This segmentation allows different portions of the control gate to serve different purposes - one side for interconnect formation and the other for selective gate removal, thereby improving ease of manufacture.
2Ease of manufacture
If gate strap regions with projections are formed on control gates, then interconnect formation is facilitated, but manufacturing precision requirements increase
Solution Approach 1:
The gate strap regions with projections are formed as preliminary structures during the gate stack formation process, before subsequent patterning and etching steps. This preliminary configuration of projections provides built-in alignment features that guide subsequent manufacturing steps, reducing the precision requirements for later alignment-critical operations such as contact hole formation and select gate removal.
Data Source
AI summary
Structures for a flash memory cell array and methods of forming a structure for a flash memory cell array. The structure comprises a first gate stack including a first control gate and a second gate stack including a second control gate. The first control gate has a first sidewall, a second sidewall opposite from the first sidewall, and a gate strap region, and the gate strap region includes a projection extending outwardly from the first sidewall of the first control gate. The second control gate has a first sidewall and a second sidewall opposite from the first sidewall, and the second sidewall of the second control gate faces the second sidewall of the first control gate.