Control Path Redundancy for Peripheral Functional Safety
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Solution Overview
Problem
Computing hardware in safety-critical applications faces challenges in maintaining fault tolerance due to single event upsets, which can cause data corruption and errors, and completely duplicating hardware is expensive.
Innovation Solution
A circuit and method implementing control path redundancy using primary and secondary register circuitry, a counter, and a controller to detect and verify signal consistency within a set time, asserting safety warnings or resetting when inconsistencies occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If completely duplicating computing hardware is used to provide fault tolerance, then reliability is improved, but cost increases
Solution Approach 1:
The patent segments the redundancy requirement into two distinct paths: a fast control path for time-critical operations and a secondary path for verification. This segmentation allows the system to achieve fault tolerance without completely duplicating the entire hardware, as only critical control signals need redundant verification while data paths can use simpler protection mechanisms.
Solution Approach 2:
The patent implements preliminary verification by checking control signals before they are executed. The secondary path receives and verifies control signals in advance, comparing them against expected values or redundant copies. This preliminary action detects errors before they propagate through the system, maintaining reliability without requiring full hardware duplication.
2Reliability
If control path redundancy is implemented with timing verification, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses periodic timing checks where the secondary path verifies control signals at specific intervals or within defined time windows. This periodic verification approach provides systematic fault detection without requiring continuous complex monitoring, balancing reliability improvement with acceptable circuit complexity.
Solution Approach 2:
The patent introduces intermediary verification logic that acts as a mediator between the primary control path and the execution units. This intermediary layer checks control signals for validity and timing without requiring full duplication of control logic, thereby improving reliability while limiting the increase in overall device complexity.
Data Source
AI summary
A circuit includes primary register circuitry to receive a first signal to write a first value to the primary register circuitry; secondary register circuitry to receive a second signal to write a second value to the secondary register circuitry; a counter configured to count a set amount of time from when the first signal is received; and a controller coupled to the counter. The controller receives at least one of: a third signal indicating whether the second signal was detected within the set amount of time, and a fourth signal indicating whether the first value is the same as the second value.