Control Queue Phase Buffering Bit-by-Bit
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Solution Overview
Problem
Existing phase-buffering solutions, such as FIFOs, face challenges in managing the control-to-data bundling constraint and are inefficient when dealing with spatially distributed input data, requiring additional delay margins that slow down stages and increase the number of stages needed for effective phase buffering.
Innovation Solution
A system utilizing a control queue with stages configured to accept mutually exclusive control signals, where one signal indicates a data bit is zero and the other indicates it is one, allowing for efficient phase-buffering on a bit-by-bit basis using forward and reverse transfer mechanisms, and incorporating asP* circuitry with specific gate delays and inversion loops for robust operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FIFO-based phase buffering is used, then data can be buffered between clock domains, but the control-to-data bundling constraint requires additional delay margins that slow down operation and increase the number of stages needed
Solution Approach 1:
The invention segments the data path into individual bit-wide channels, with each bit having its own independent control signals (ready and acknowledge). This eliminates the need for control-to-data bundling since control signals are no longer coupled with data bits, allowing each bit to be processed independently at high speed without delay margins.
Solution Approach 2:
The invention extracts the control signals (ready and acknowledge) from the data path, separating them into independent control queues. This extraction eliminates the bundling constraint entirely, as control signals are now completely decoupled from data bits and can operate independently to manage phase buffering without slowing down data transfer.
2Reliability
If traditional FIFO-based phase buffering is used, then data can be buffered between clock domains, but the number of stages required increases for a specified amount of phase buffering
Solution Approach 1:
By segmenting the buffering into independent bit-wide channels with separate control queues, each stage can provide maximum phase buffering capability. The segmentation allows parallel processing of multiple bits through the same number of stages, reducing the total number of stages needed compared to bundled FIFO approaches.
Solution Approach 2:
The invention uses dynamic control queues where the ready and acknowledge signals can independently control the flow of each bit. This dynamic control allows flexible phase adjustment without requiring additional fixed stages, enabling the same buffering capability with fewer configurable stages.
3Loss of information
If control signals are bundled with data bits in traditional FIFO, then data validity can be announced, but the bundling delay constraint requires careful circuit design and layout to ensure correct timing
Solution Approach 1:
The invention extracts control signals from the data path, placing them in separate control queues. This extraction completely eliminates the bundling delay constraint, as control signals no longer share physical paths with data bits. The control queues independently manage data validity signaling without requiring careful timing coordination between control and data paths.
Solution Approach 2:
The control queue acts as an intermediary between the data source and data destination, independently managing control signals. This intermediary structure allows control signals to be generated and processed separately from data bits, eliminating the need for tight timing coordination and reducing circuit design complexity.
Data Source
AI summary
One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the control queue is configured to accept both a first control signal and a second control signal, wherein the first control signal and the second control signal are mutually exclusive, wherein the first control signal being asserted indicates the value of a corresponding bit is zero, while the second control signal being asserted indicates the value of the corresponding bit is one. A forward-transfer mechanism couples the first control signal or the second control signal from the input of the stage through storage elements to the output of the stage. A reverse transfer mechanism accepts an acknowledgement signal at the output of the stage and transfers the acknowledgement signal through a storage element to the input of the stage.