Mode-Dependent Control Signal Timing to Prevent Reset-Write Overlap
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Solution Overview
Problem
Conventional semiconductor memory devices experience power dissipation due to overlapping reset and write-enable signal periods, leading to leakage current, and face challenges in timing margins and operation rates during mode changes from writing to reading operations.
Innovation Solution
A control signal generation circuit that includes a pulse signal generator to delay column control signals differently, generating distinct pulse signals for reset and write-enable signals based on a write/read flag, thereby preventing signal overlap and optimizing signal timings for reduced power consumption and improved operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the reset signal LIORST and write-enable signal BWEN are generated by delaying the column control signal YICTRL through delay paths, then the control signals are generated in response to the column control signal, but the reset and write-enable signals overlap in enabling term causing leakage current and power dissipation
Solution Approach 1:
The patent applies dynamics by making the delay time variable rather than fixed. The delay time for generating the reset signal is dynamically adjusted based on the operation mode (reading or writing) through mode-dependent delay circuits. This allows the control signals to be generated at optimal times for each operation mode, preventing overlap and leakage current while maintaining ease of operation.
Solution Approach 2:
The patent changes the parameter of delay time based on operation mode. Different delay times are applied for reading operations versus writing operations. By changing this critical parameter dynamically, the patent prevents the overlapping of reset and write-enable signals that causes power dissipation, while still maintaining proper control signal generation functionality.
2Reliability
If the sensing start time of the bit-line sense amplifier BLSA is delayed to avoid sensing fail due to noise during mode change, then sensing reliability is improved, but the operation rate becomes lower
Solution Approach 1:
The patent applies preliminary action by performing precharging of the local input/output line pair before the sensing operation, especially during mode changes. The reset signal is generated with appropriate timing to ensure precharging is completed before sensing starts. This preliminary precharging action prepares the circuit in advance, allowing sensing to start earlier without risking noise-induced sensing failures, thus maintaining both reliability and operation rate.
3Reliability
If the reset signal LIORST enabling period is extended to ensure sufficient timing margin for precharging during reading operation, then precharging reliability is improved, but the timing margin for writing operation may be reduced
Solution Approach 1:
The patent applies dynamics by implementing mode-dependent delay circuits that dynamically adjust the reset signal timing based on whether the operation is reading or writing. For reading operations, the reset signal enabling period is extended to ensure sufficient precharging time. For writing operations, the delay is adjusted to maintain appropriate timing margins. This dynamic adjustment resolves the contradiction by optimizing timing for each specific operation mode.
Data Source
AI summary
A control signal generation circuit includes a pulse signal generator configured to delay a column control signal by delay times different from each other and to generate first and second pulse signals, a reset signal generator configured to transfer alternatively the first and second pulse signals as a reset signal in response to a write/read flag signal, and a write-enable signal generator configured to generate a write-enable signal from the first pulse signal in response to the write/read flag signal.