Control Signal Timing Correction for EtherCAT Synchronization
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Solution Overview
Problem
In EtherCAT systems, synchronization errors can occur between the synchronization signal and control signal generated by separate processors, leading to desynchronization of operations among slaves, which can disrupt the coordination of control target objects like motors.
Innovation Solution
A control device with a first processor acquiring the synchronization signal and a second processor generating the control signal, where the second processor corrects timing errors by adjusting the timer width to align the control signal with the synchronization signal, minimizing disruptions and stabilizing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the synchronization signal and control signal are generated by separate processors, then the system can operate with higher processing capacity and flexibility, but timing errors will gradually accumulate between the signals
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors the timing difference between the synchronization signal and control signal, and automatically adjusts the timer width to correct accumulated timing errors. This closed-loop control ensures that separate processors can operate independently while maintaining synchronization through real-time error detection and correction.
Solution Approach 2:
The patent dynamically changes the timer width parameter to compensate for timing drift between separate processors. By adjusting this parameter based on detected timing errors, the system maintains synchronization while allowing the processors to operate independently with their own clocks and processing cycles.
2Measurement precision
If timing errors are corrected frequently to maintain synchronization, then synchronization accuracy is improved, but the impact on sub-processors increases
Solution Approach 1:
The patent implements dynamic correction where the timing adjustment is applied selectively to future timer operations rather than immediately affecting all ongoing sub-processor operations. This dynamic approach allows synchronization correction to be performed while minimizing disruption to running sub-processors, as the correction is gradually applied through adjusted timer widths in subsequent cycles.
3Reliability
If the timer width is adjusted to correct timing errors, then synchronization is restored, but the system complexity increases
Solution Approach 1:
The patent implements a self-correcting mechanism where the system automatically detects timing errors and adjusts its own timer width without requiring external intervention or complex control systems. The error detection and correction functionality is integrated into the existing processor operations, allowing the system to self-regulate synchronization while minimizing additional complexity.
Data Source
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Figure 2A~2B
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AI summary
A control device includes a first processor that acquires a synchronization signal that is generated every first period, and a second processor that generates a second period that is obtained by dividing the first period by n (n ≥ 1), generates a control signal, using a timer, every third period that is obtained by dividing the second period by m (m ≥ 2), where at least one of a plurality of control signals generated in the first period is a control signal that should be synchronous with the synchronization signal, and in a case where occurrence of an error between timings of the synchronization signal and the control signal that should be synchronous with the synchronization signal is detected, the second processor corrects the error by temporarily changing a width of the timer that is to be started at next and later times.