Time-Triggered Control Slot Sizing With Anytime Algorithms

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Solution Overview

Problem

In time-triggered controllers, determining the optimal duration for computational actions is challenging due to inherent temporal indeterminism in hardware and algorithmic complexity, leading to over-dimensioned slot lengths and unused time intervals, while reducing slot duration increases impreciseness and model error.

Innovation Solution

Deployment of anytime algorithms with a core and enhancing segments, where the slot length is determined by probing multiple durations to balance impreciseness and model error, ensuring a satisficing result within the given slot, and using state-of-the-art WCET analysis to establish minimum and maximum execution slot durations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the slot length for computational actions is increased, then the control algorithm can deliver more precise results, but the unused time interval increases and productivity decreases

Engineering Contradiction:
Improvecontrol algorithm precisionVSAvoidsystem productivity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies dynamics by making the slot length adjustable rather than fixed. The control unit dynamically adapts the slot length for computational actions based on actual execution needs, allowing the system to optimize between precision and productivity by allocating more time when needed and less time when sufficient results are achieved earlier.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the slot length for computational actions is decreased, then productivity increases and unused time is reduced, but the impreciseness and model error increase

Engineering Contradiction:
Improvesystem productivityVSAvoidcontrol algorithm precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The control unit dynamically adjusts the slot length based on runtime conditions and algorithm progress. This allows the system to use shorter slots when possible to improve productivity while maintaining sufficient precision, and extend slots when higher precision is needed, resolving the contradiction between these two parameters.

Inventive Principle:
Principle #15Dynamics

3Reliability

If WCET analysis is used to determine slot length, then reliability is improved, but the slot length becomes over-dimensioned and loses time efficiency

Engineering Contradiction:
Improvetemporal determinismVSAvoidunused execution time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the computational action into core functionality and optional enhancement parts. The control unit determines a minimum slot length sufficient for reliable operation and an optional extended slot length for optimization. This segmentation allows the system to maintain reliability through the minimum slot while reducing time loss by not always allocating the maximum over-dimensioned slot.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of slot length from a single fixed value determined by WCET analysis to a range of possible values. The control unit selects from this range based on actual runtime conditions, allowing the system to maintain reliability (by never going below the minimum) while minimizing time loss (by selecting the smallest sufficient slot).

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3467598B1Method and apparatus for the determination of the slot-duration in a time-triggered control system
Publication Date: 2021.09.29 TTTECH COMPUTERTECHNIK AG
  • EP3467598B1 patent drawingFigure 1
  • EP3467598B1 patent drawing
  • EP3467598B1 patent drawing

AI summary

Method for a determination of the optimal duration of a time slot for computational actions in a time-triggered controller, the controller comprising a sensor subsystem, a computational subsystem, an actuator subsystem and a time-triggered communication system, wherein the time-triggered communication system is placed between the sensor subsystem, the computational subsystem, the actuator subsystem and the monitor subsystem, wherein an anytime algorithms is executed in the computational subsystem, and wherein a plurality of execution slot durations of the anytime algorithms is probed during the development phase, starting from the minimum execution slot duration, increasing this slot duration by the execution slot granularity until the maximum execution slot duration is reached, and wherein in each one of the execution slot durations a multitude of frames is executed in a destined application environment, and wherein in each frame the computational subsystem calculates imprecise anticipated values of observable state variables by interrupting the execution of the anytime algorithm at the end of the provided execution slot duration, using data received from the sensor subsystems at the beginning of the frame, and wherein in each frame the monitor subsystem calculates the precise anticipated values of observable state variables by executing the anytime algorithm until completion using data received from the sensor subsystems at the beginning of the frame, and wherein the monitor subsystem computes an anytime-algorithm impreciseness by calculating the absolute values of the respective difference between these precise anticipated values of observable state variables and the imprecise anticipated values of observable state variables contained in the messages delivered from the computational subsystems to the monitor subsystem at the end of the frame, and wherein the monitor subsystem computes a model error by calculating the absolute values of the difference between these precise anticipated values of observable state variables and the respective acquired values of observable state variables contained in messages from the sensor subsystem to the monitor subsystem at the end of the frame, and wherein an average anytime-algorithm impreciseness and an average model error of a slot duration are calculated by the monitor subsystem by averaging the results of the multitude of probed frames of the slot, and wherein at the end of the development phase an execution slot duration for the computational subsystem is selected out of the probed execution slot durations, wherein the sum of the average model error and the average anytime-algorithm impreciseness is minimal.