Control Wafer Charge Accumulation Measurement

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Solution Overview

Problem

The semiconductor integrated circuit (IC) industry faces challenges in monitoring and managing charge accumulation during fabrication, which can lead to reliability issues and requires effective methods to ensure the operability of semiconductor devices.

Innovation Solution

A method involving the fabrication of control and reference transistors on a substrate with different well regions, where charge accumulation is measured by evaluating electrical parameters, allowing for precise determination of charge accumulation and ensuring device operability through a wafer acceptance test (WAT), with the control transistor reflecting charge accumulation in one well region and the reference transistor in another, enabling the identification of inoperable wafers and guiding the design of device wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If charge accumulation is monitored during fabrication, then reliability issues can be detected, but measurement precision and detection difficulty are challenged

Engineering Contradiction:
Improvedevice operabilityVSAvoidcharge accumulation measurement
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

A control wafer with control transistors is introduced as an intermediary to indirectly measure charge accumulation. The control transistors are placed in different well regions than the device transistors, allowing charge accumulation effects to be measured separately and then correlated to device performance without directly measuring the charge itself in the device regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control wafer creates a copy of the device wafer structure with identical processing but different transistor configurations. By measuring electrical parameters (threshold voltage, drive current) of the control transistors, the charge accumulation effects are replicated and measured, providing a proxy measurement for the actual device regions where direct measurement is difficult.

Inventive Principle:
Principle #26Copying

2Productivity

If device feature size is scaled down to increase functional density, then productivity and performance improve, but charge accumulation issues become more severe

Engineering Contradiction:
Improveproduction efficiencyVSAvoidcharge accumulation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The control wafer measurements are performed during the fabrication process itself, before device wafers are finalized. This preliminary detection of charge accumulation trends allows process adjustments to be made proactively, preventing reliability issues from developing in the scaled-down devices before they are completed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Electrical parameters from control transistors (threshold voltage shifts, drive current changes) provide real-time feedback about charge accumulation during fabrication. This feedback loop enables process engineers to adjust fabrication parameters to compensate for charge accumulation effects, maintaining reliability even as device dimensions are scaled down for higher productivity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11107737B2Control wafer and method for fabricating semiconductor device
Publication Date: 2021.08.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11107737B2 patent drawing
  • US11107737B2 patent drawing
  • US11107737B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.