Controller Logical Address Mapping for Memory Copy Optimization
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Solution Overview
Problem
Current memory systems face inefficiencies in managing logical addresses and data storage regions, leading to suboptimal performance and resource utilization during data copy operations.
Innovation Solution
A controller method that determines whether a second copy event will occur based on thresholds for invalid pages, erase operations, and error frequencies, and adjusts logical addresses accordingly, either invalidating or mapping them without substantial data copying when such events are unlikely.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller performs substantial data copying during logical address changes, then data integrity is maintained, but data access speed deteriorates
Solution Approach 1:
The patent uses logical address mapping (a form of copying) instead of physical data copying. The controller maintains a mapping table that associates logical addresses with physical addresses, allowing data to be accessed through address translation without moving the actual data. This resolves the contradiction by providing fast access (like copying) while maintaining data integrity through the mapping mechanism.
Solution Approach 2:
The patent introduces a mapping table as an intermediary between logical addresses and physical addresses. This intermediary structure allows the system to translate addresses without performing substantial data copying operations, thereby maintaining both data integrity and fast access speeds.
2Manufacturing precision
If the controller performs substantial data copying during address management operations, then address mapping accuracy is maintained, but productivity deteriorates
Solution Approach 1:
The patent uses logical address mapping to create virtual copies of address references without copying actual data. This allows the controller to manage addresses efficiently while maintaining mapping accuracy through the mapping table structure, significantly improving productivity compared to substantial data copying.
Solution Approach 2:
The patent performs preliminary address mapping operations by maintaining a mapping table that pre-establishes relationships between logical and physical addresses. This preliminary action allows subsequent data operations to proceed without performing substantial copying, thereby improving productivity while maintaining address mapping accuracy.
3Adaptability or versatility
If the controller performs frequent data copying operations, then address management flexibility is improved, but loss of time increases
Solution Approach 1:
The patent uses logical address copying through the mapping table instead of physical data copying. This approach provides address management flexibility by allowing logical addresses to be remapped without moving data, while eliminating the time loss associated with substantial data copying operations.
Solution Approach 2:
The patent establishes preliminary address mappings in the mapping table, which allows flexible address management to be achieved through simple table updates rather than time-consuming data copying operations. This preliminary action significantly reduces the time loss while maintaining adaptability.
Data Source
AI summary
In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.