Duplexed Controller Bridge Failure Detection and Arbitration
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Solution Overview
Problem
In storage apparatuses with duplexed controller modules, errors in one module can incorrectly identify a second module as failing, leading to unnecessary shutdowns, especially due to issues like PCIe bridge failures, which can result in undetected error data being written to memory.
Innovation Solution
A method where data is transmitted between controller modules through PCIe bridges, with error detection and retransmission mechanisms to determine the source of failures, ensuring that only the faulty module is shut down and preventing error data from being written to memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection is performed in duplexed CMs, then reliability is improved, but false failure identification causes unnecessary shutdowns
Solution Approach 1:
The patent introduces a third CM (CM #2) as an intermediary to act as an arbiter between conflicting failure detections. When CM #0 and CM #1 both detect failures, CM #2 receives failure detection results from both and determines the actual failure source, preventing false shutdowns of functional CMs while maintaining high reliability through accurate fault identification
2Reliability
If isolation processing is performed upon failure detection, then fault containment is improved, but false positives lead to unnecessary CM shutdowns
Solution Approach 1:
The patent implements a feedback mechanism where failure detection results are sent to both the detecting CM and the third CM. The third CM provides feedback about the actual failure source based on results from multiple CMs, allowing the system to confirm true failures before executing isolation processing, thereby reducing false positives while maintaining effective fault containment
3Speed
If data is written to memory during error transmission, then processing speed is maintained, but error data may be inadvertently written to memory
Solution Approach 1:
The patent performs preliminary detection of PCIe bridge failures before data is written to memory. By detecting errors in the transmission path ahead of time and identifying the failure source through the third CM, the system can prevent error data from being written to memory while maintaining normal processing speeds for valid data through continuous error monitoring and source identification
Data Source
AI summary
A first controller stores externally input data to a memory of the first controller, reads data stored in the memory of the first controller and transmits the data to a second controller through a first controller bridge, detects a failure at the first controller bridge in transmission of the data. The second controller receives the data through a second controller bridge, writes the received data into a memory of the second controller, and determines whether the failure is caused by the first controller if a failure occurs in the memory controller and the second controller bridge. If a failure is detected in the first controller and the second controller and the failure is caused by the first controller, the first controller transmits the data causing the failure during transmission through the first controller bridge and the second controller receives the data through the second controller bridge.