Controller-bridge Architecture for NVM Latency Reduction
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Solution Overview
Problem
Current controller architectures for solid-state drives (SSDs) face limitations in managing high-level NVM functions such as garbage collection, wear leveling, and logical-to-physical mapping efficiently, while also requiring improved data throughput and latency reduction, especially with evolving NAND technologies that have reduced endurance.
Innovation Solution
A controller-bridge architecture is proposed where the controller handles high-level NVM management functions like garbage collection, wear leveling, and logical-to-physical mapping over a high-speed interface like PCIe, while the bridge performs basic signal processing and channel management, allowing for optimized design updates and power management, and enabling direct page-level control of NVM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional controller architecture is used to manage high-level NVM functions, then the controller can perform garbage collection, wear leveling, and logical-to-physical mapping, but the data throughput performance and latency are insufficient
Solution Approach 1:
The system is divided into two independent components: a controller that handles high-level NVM management functions (garbage collection, wear leveling, logical-to-physical mapping) and a bridge device that handles basic signal processing and channel management. This segmentation allows each component to be optimized independently, with the bridge device providing high-speed direct access to NVM while the controller manages complex operations, thereby improving data throughput and reducing latency.
Solution Approach 2:
The bridge device acts as an intermediary between the controller and the NVM. It receives commands from the controller, performs basic signal processing and channel management, and directly accesses the NVM without requiring the controller to handle low-level operations. This intermediary architecture enables high-speed data transfer while the controller focuses on high-level management, resolving the throughput-latency contradiction.
2Adaptability or versatility
If the controller handles all NVM management functions including basic signal processing, then functionality is integrated, but device complexity and power consumption increase
Solution Approach 1:
The NVM management functionality is segmented into two distinct components: the controller handles high-level functions (garbage collection, wear leveling, logical-to-physical mapping) while the bridge device handles basic signal processing and channel management. This segmentation reduces the complexity of each individual component while maintaining comprehensive NVM management capabilities, as each component has a specialized, optimized function set.
Solution Approach 2:
The bridge device is designed with multi-functionality to handle various basic operations (signal processing, channel management, direct NVM access) while the controller handles high-level management functions. This universal design allows the system to adapt to diverse NVM products and hybrid drives without increasing overall complexity, as each component can be independently optimized for its specific function set.
3Reliability
If the controller directly manages all NVM operations, then control is centralized, but power consumption increases
Solution Approach 1:
The control management functionality is segmented between the controller and bridge device. The bridge device, which consumes less power, handles basic signal processing and direct NVM access operations. The controller, which can be in lower-power states, handles high-level management functions. This segmentation allows the system to maintain reliable NVM control while minimizing overall power consumption by keeping the higher-power controller inactive during simple operations.
Solution Approach 2:
The bridge device performs self-service by handling basic signal processing and channel management independently without requiring the controller to be active. It can directly access the NVM and manage basic operations autonomously, reducing the need for the controller to wake from low-power states and thereby reducing overall system power consumption while maintaining control reliability.
Data Source
AI summary
Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface. The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller includes a volatile memory (e.g., DRAM) that stores parameters related to the operation of the NVM as provided by the bridge. The parameters may be related to optimizing use of the NVM and are automatically appended by the controller to appropriate data storage commands to the bridge. The parameters may be stored in a table format in which each entry is indexed by a physical address of the NVM.