Controller-Bridge Architecture for SSD Latency and Power Optimization
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Solution Overview
Problem
Current controller architectures for solid-state drives (SSDs) face limitations in managing high-level functions such as garbage collection, wear leveling, and logical-to-physical mapping, while also requiring efficient data throughput, which are not adequately addressed by existing standards like ONFI, leading to performance bottlenecks and increased latency.
Innovation Solution
A controller-bridge architecture is proposed, where the controller handles high-level NVM management functions like garbage collection and wear leveling using a high-speed interface like PCIe, while the bridge performs lower-level tasks like channel management and signal processing, allowing for optimized design constraints and power management, enabling direct page-level control and unified address management across different storage media.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a controller handles high-level NVM management functions (garbage collection, wear leveling, mapping), then data throughput performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The system is divided into two separate components: a controller that handles high-level NVM management functions (garbage collection, wear leveling, logical-to-physical mapping) and a bridge that handles lower-level tasks (channel management, signal processing). This segmentation allows each component to be optimized independently, with the controller focusing on complex data management algorithms while the bridge handles raw signal interfacing, thereby managing overall system complexity while maintaining high productivity.
Solution Approach 2:
The bridge acts as an intermediary component between the host interface and the NVM array. It mediates the communication by handling channel management and signal processing tasks, allowing the controller to focus exclusively on high-level management functions without being burdened by low-level signal processing, thus improving data throughput while managing complexity through functional separation.
2Productivity
If a controller handles high-level NVM management functions, then data throughput performance is improved, but power consumption increases
Solution Approach 1:
By segmenting the system into a power-efficient bridge handling low-level signal processing and a controller handling high-level management, each component can be optimized for its specific function. The bridge can enter low-power states during idle periods while maintaining readiness, and the controller can batch process management tasks to minimize active power consumption, collectively achieving high throughput with reduced overall power usage compared to a monolithic controller design.
3Ease of manufacture
If ONFI standard interface is used for flash memory control, then ease of manufacture is improved, but functionality for high-level management is insufficient
Solution Approach 1:
The system separates the standardized ONFI interface functionality (handled by the bridge for ease of manufacture) from the high-level management functionality (handled by the controller). This allows the bridge to use the well-established ONFI standard for reliable flash memory interfacing while the controller implements sophisticated management algorithms, achieving both manufacturing ease and advanced functionality.
Solution Approach 2:
The bridge serves as an intermediary that implements the standardized ONFI interface, providing a reliable and easily manufactured connection to flash memory devices. It translates standardized ONFI commands into controller-specific instructions, enabling the controller to implement advanced high-level management functions without being constrained by the limitations of the basic ONFI command set.
Data Source
AI summary
Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.