Controller Memory Buffer Caching for Chunk-Level AI Inference Writes
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Solution Overview
Problem
Existing memory sub-systems face inefficiencies during artificial intelligence inference due to the need to transfer entire logical block addresses, which exceed the required data size, leading to wasted host memory capacity and reduced efficiency.
Innovation Solution
Implementing a memory sub-system controller memory buffer (CMB) that allows direct access and caching of smaller data chunks, enabling efficient data transfer and utilization within the host system without requiring double buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If entire logical block addresses are transferred during AI inference, then data completeness is ensured, but host memory capacity is wasted and efficiency is reduced
Solution Approach 1:
The patent segments the logical block address into two parts: a first portion stored in the controller's buffer memory and a second portion stored in the host system's memory. This segmentation allows the host to only store the necessary second portion rather than the entire logical block address, reducing host memory consumption while maintaining the ability to retrieve complete data when needed.
2Speed
If controller memory buffer is used for data caching, then data access speed is improved, but device complexity increases
Solution Approach 1:
The controller memory buffer serves multiple functions: it stores the first portion of logical block addresses, caches data for AI inference operations, and enables efficient data transfer between the host system and storage device. By making the buffer multi-functional, the patent avoids adding separate dedicated components, thereby limiting the increase in device complexity while achieving improved data access speed.
Data Source
AI summary
A processing device in a memory sub-system stores a block of data from a non-volatile memory device of the memory sub-system in a controller memory buffer, the block of data comprising a plurality of chunks of data, wherein the memory sub-system comprises a volatile memory device with a first portion configured as the controller memory buffer. The processing device further provides a first chunk of data of the plurality of chunks of data from the controller memory buffer to a host system, receiving, from the host system, a write command and a modified chunk of data, the modified chunk of data comprising at least one modification to the first chunk of data, and writes the modified chunk of data to the block of data in the controller memory buffer.