Controller Cache Management for Nonvolatile Memory Systems

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory systems face inefficiencies in managing mapping information in cache memory, leading to suboptimal performance and increased power consumption in portable electronic devices.

Innovation Solution

A memory system with a nonvolatile memory device and a controller that stores commands in a command queue, manages mapping information by selecting and removing partial mapping information from the internal cache memory using a predetermined selection algorithm, and assigns physical addresses based on logical addresses, optimizing cache memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If mapping information is stored in internal cache memory to improve data access rate, then access speed is improved, but power consumption increases and cache memory becomes full requiring management overhead

Engineering Contradiction:
Improvedata access rateVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by storing only a portion of mapping information in the internal cache memory rather than all mapping information. The controller selectively caches mapping information based on prediction of future access patterns, storing only those entries likely to be accessed soon. This partial caching approach improves access speed for predicted operations while avoiding the power consumption and management overhead of caching all mapping information.

Inventive Principle:
Principle #16Partial or excessive action

2Speed

If more mapping information is cached in internal cache memory, then data access rate is improved, but device complexity and management overhead increase

Engineering Contradiction:
Improvedata access rateVSAvoidcache management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements self-service through automatic prediction-based caching. The controller autonomously predicts which mapping information will be accessed based on analysis of command queue patterns and automatically updates the cache accordingly. This eliminates the need for complex manual cache management algorithms (such as LRU or FIFO) and reduces management overhead while maintaining high access rates through intelligent, adaptive caching.

Inventive Principle:
Principle #25Self-service

3Productivity

If victim mapping information is selected and removed from cache, then cache memory usage is optimized, but risk of accessing uncached mapping information increases

Engineering Contradiction:
Improvecache memory efficiencyVSAvoidaccess reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by proactively loading mapping information into the cache before it is actually needed. The controller analyzes the command queue to predict future access patterns and pre-loads corresponding mapping information into the cache. This ensures that when mapping information is evicted from the cache, the predicted access patterns guarantee that needed entries remain cached, eliminating access reliability issues while maintaining high cache efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10762001B2Memory system and operation method thereof
Publication Date: 2020.09.01 SK HYNIX INC
  • US10762001B2 patent drawing
  • US10762001B2 patent drawing
  • US10762001B2 patent drawing

AI summary

A memory system includes a nonvolatile memory device including a plurality of memory blocks; and a controller including a command queue adapted to store a plurality of commands from the host, wherein the controller is suitable for managing mapping information for mapping logical addresses of the commands to physical addresses of the nonvolatile memory device, storing partial mapping information into an internal cache memory, storing the whole mapping information into the memory blocks, selecting a piece of victim mapping information among the partial mapping information stored in the internal cache memory, and removing the piece of victim mapping information based on logical addresses of the commands stored in the command queue.