Controller Chip-Kill Parity Update Read Latency
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Solution Overview
Problem
Current data storage apparatuses using semiconductor memory devices face challenges in error detection and correction, particularly in maintaining data integrity and reducing read latency during write operations.
Innovation Solution
The implementation of a data storage apparatus with a controller that generates and updates chip-kill parity across multiple planes, allowing for error detection and correction while maintaining data outside the device until parity updates are complete, thereby reducing read latency by not accessing parity dies during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller updates chip-kill parity during write operations by accessing parity dies, then data integrity is improved through error detection and correction, but read latency increases due to channel occupancy during parity updates
Solution Approach 1:
The controller performs preliminary actions by maintaining a pool of unused parity dies and preparing replacement parity data in advance. When a read request arrives during a write operation, the controller can immediately serve the read from the unused parity die without waiting for the write operation to complete, thus resolving the contradiction between maintaining data integrity and reducing read latency.
Solution Approach 2:
The parity storage is segmented into multiple parity dies, with at least one parity die reserved and unused during write operations. This segmentation allows the system to separate read operations from write operations, enabling reads to be served from unused parity dies while writes update chip-kill parity on other parity dies, thereby eliminating read latency penalties.
2Loss of time
If the controller maintains second data outside the data storage device during chip-kill parity updates, then read latency is reduced by avoiding parity die access, but device complexity increases due to external data maintenance
Solution Approach 1:
The controller acts as an intermediary by maintaining second data in its internal memory or buffer. Instead of directly accessing parity dies for every read operation during write updates, the controller intermediates by serving reads from its internal storage, thus reducing read latency while managing the complexity of data maintenance centrally in the controller.
3Reliability
If multiple parity dies are used to store second data and chip-kill parity, then error detection and correction capability is improved, but channel occupancy time increases during write operations
Solution Approach 1:
The system performs preliminary actions by pre-positioning unused parity dies and preparing replacement data before read requests arrive. This allows the channel to be released earlier for read operations without compromising error detection and correction capability, as the unused parity dies are already in place and ready to serve read requests independently of the ongoing write operations.
Data Source
AI summary
A data storage apparatus may include a data storage device including at least one data die to store first data, and at least one parity die to store second data, third data, and a chip-kill parity, where the at least one data die and the at least one parity die are connected to a channel, and controller in communication with the data storage device and configured to receive a write request for the first data and the second data from a host that is in communication with the data storage device through the channel to generate the chip-kill parity from the first data and the second data. The controller is further configured to read the third data from the parity die and provide the third data to the host upon receipt of a read request for the third data from the host while the chip-kill parity is being updated based on the first data.