Programmable Controller Communication Unit Cache Memory
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Solution Overview
Problem
In network systems for factory automation, the high-frequency data exchange between programmable controllers leads to increased bus traffic and a heavy load on the CPU unit, making it difficult to achieve both high-speed control and high-speed data exchange simultaneously.
Innovation Solution
A programmable controller with a communication unit that has a bus master function, allowing direct access to the internal bus and featuring a cache memory for storing IO data, which reduces the need for CPU intervention by checking for data updates and refreshing the cache only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU unit accesses the input-output unit memory for every data exchange, then the data exchange can be performed, but the load on the CPU unit becomes heavy and control performance deteriorates
Solution Approach 1:
The invention extracts the I/O access function from the CPU unit and assigns it to the communication unit. The communication unit is equipped with a bus master function that enables it to independently access the I/O memory without CPU intervention. This extraction resolves the contradiction by allowing high-frequency data exchange through the communication unit while the CPU unit focuses on control tasks, thereby reducing CPU load while maintaining or improving data exchange productivity.
2Device complexity
If the communication unit directly accesses the I/O memory, then the CPU load is reduced, but the bus traffic increases and affects both communication and control units
Solution Approach 1:
The invention implements a cache memory in the communication unit that preliminarily stores copies of I/O data. Before actual data exchange occurs, the communication unit checks whether the required data is already present in the cache. If found, the data is used directly without accessing the I/O memory through the bus. This preliminary action reduces bus traffic while still allowing the communication unit to independently handle data exchange, thus reducing CPU load without overwhelming the bus system.
3Speed
If high-speed data exchange is implemented, then the data exchange cycle speed increases, but the bus traffic suddenly increases and affects system stability
Solution Approach 1:
The cache memory performs preliminary storage of I/O data, allowing the communication unit to serve multiple data exchange requests from cache without generating proportional bus traffic. This preliminary action enables high-speed data exchange cycles while smoothing out bus traffic fluctuations, as the bus is only actively used when cache data needs to be refreshed, not for every data exchange operation.
Solution Approach 2:
The invention implements periodic refresh of the cache memory rather than continuous bus access for every data request. The cache is refreshed at predetermined intervals or when data changes are detected, while data exchange can occur continuously from the cache. This periodic action maintains high data exchange speeds while creating a more stable and predictable bus traffic pattern that doesn't overwhelm the system.
Data Source
AI summary
A programmable controller includes a CPU unit, a communication unit and peripheral units connected together through an internal bus. The communication unit has a bus master function, including a cache memory for recording IO data stored in the memory of an input-output unit. When a message is received, it is judged whether the IO data stored in the memory of the input-output unit specified by this message is updated or not. If the data are not updated, a response is created based on the IO data stored in the IO data stored in the cache memory. If the data are updated, the input-output unit is accessed and updated IO data are obtained and a response is created based on the obtained IO data.