Controller for Data Storage Device Using Cost-Based Page Replacement

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Solution Overview

Problem

Conventional hard disk drives (HDDs) are vulnerable to mechanical failures, vibrations, and noise due to their mechanical components, while solid state disks (SSDs) offer higher reliability and speed but face inefficiencies in data management and storage performance.

Innovation Solution

A data storage device with first and second main memories, a buffer memory, and a controller that programs data from the buffer memory to the main memories, using a cost-based page replacement technique to optimize data transfer and scheduling, thereby maximizing channel usage and minimizing performance fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is programmed sequentially to main memories through channels, then channel usage is simple and manageable, but channel utilization efficiency deteriorates due to idle waiting time

Engineering Contradiction:
Improvechannel utilization efficiencyVSAvoiddata scheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The controller pre-prepares multiple victim cache lines in the buffer memory before channel operations begin. When a channel becomes idle after completing a programming operation, the controller can immediately initiate programming to another cache line without waiting for data preparation, thus eliminating channel idle time and improving utilization efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller ensures continuous programming operations by maintaining multiple ready-to-program victim cache lines in the buffer memory. This allows channels to perform programming operations back-to-back without idle periods, achieving continuous useful action and maximizing channel utilization efficiency despite increased scheduling complexity.

Inventive Principle:
Principle #20Continuity of useful action

2Reliability

If victim cache lines are programmed one after another, then programming order is simple to manage, but performance fluctuations increase due to channel idle time

Engineering Contradiction:
Improveperformance stabilityVSAvoidvictim cache line management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple victim cache lines are pre-selected and prepared in the buffer memory before channel programming operations begin. This preliminary preparation ensures that when channels complete their operations, ready-to-program cache lines are immediately available, eliminating performance fluctuations caused by channel idle time while managing complexity through structured pre-preparation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller monitors channel operation status and dynamically adjusts the selection and programming of victim cache lines based on real-time feedback. This feedback mechanism ensures stable performance by responding to channel availability, though it increases the complexity of victim cache line management through dynamic decision-making.

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If buffer memory usage is allowed to grow freely, then data storage capacity is maximized, but bottlenecks increase due to excessive data management overhead

Engineering Contradiction:
Improvebuffer memory storage capacityVSAvoiddata processing efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The controller dynamically adjusts the threshold value for buffer memory usage based on system conditions and channel availability. By changing this parameter, the system can optimize between storing more victim cache lines to improve channel utilization versus limiting buffer usage to reduce management overhead and bottlenecks, thus balancing storage capacity with processing efficiency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8555000B2Data storage device and data storing method thereof
Publication Date: 2013.10.08 SAMSUNG ELECTRONICS CO LTD
  • US8555000B2 patent drawing
  • US8555000B2 patent drawing
  • US8555000B2 patent drawing

AI summary

A data storage device and a data storing method thereof, including first main memories coupled to a plurality of channels, second main memories coupled to the plurality of channels in common, a buffer memory temporarily storing data to be programmed to the first and the second main memories; and a controller configured to program data of victim cache lines from the buffer memory to the second main memories while data of a first victim cache line from the buffer memory is being programmed to the first main memories. The storing method includes that a victim cache line is selected based on cost-based page replacement.