Controller HPB Data Management for Memory Block Optimization

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Solution Overview

Problem

Current memory systems face challenges in optimizing performance due to limited management of memory blocks and inefficient data migration, leading to reduced operational efficiency and storage capacity utilization.

Innovation Solution

The proposed solution involves generating High Performance Booster (HPB) data based on Logical to Physical (L2P) map data, storing it in memory blocks, and migrating data to other blocks when empty pages are scarce, with caching in the host memory to enhance operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If L2P map data is stored in the memory system, then data retrieval is enabled, but memory capacity is consumed and access speed decreases

Engineering Contradiction:
Improvedata access speedVSAvoidmemory capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent extracts frequently accessed L2P map data from the nonvolatile memory device and stores it in the host's volatile memory (HPB cache). This separation allows the memory system to maintain fast access to hot data while preserving nonvolatile memory capacity for other purposes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host memory acts as an intermediary between the host processor and the nonvolatile memory device. It caches L2P map data to provide fast access while the nonvolatile memory device maintains the authoritative copy, resolving the trade-off between speed and capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If HPB data is cached in the host, then access speed improves, but data consistency management becomes complex

Engineering Contradiction:
Improveaccess speedVSAvoiddata consistency management
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory system monitors HPB cache status and initiates synchronization operations when inconsistencies are detected. The host is notified of L2P map changes, enabling it to update its cache, creating a feedback loop that maintains data consistency.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system proactively manages HPB cache validity by tracking L2P map changes and initiating synchronization before consistency issues affect operations. This preliminary action prevents data inconsistency rather than reacting to it.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If memory blocks are continuously used for L2P map storage, then data retrieval is maintained, but empty pages become scarce and performance degrades

Engineering Contradiction:
Improveoperational efficiencyVSAvoidempty pages
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system extracts frequently accessed L2P map entries from the nonvolatile memory device's L2P map structure and stores them in the host's HPB cache. This reduces the amount of data that must be maintained in the memory device, preserving empty pages for other uses.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host creates a copy of frequently accessed L2P map data in its volatile memory. This copy serves the same access function for hot data, allowing the original memory device to free up space while maintaining retrieval capability.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11269765B2Operating method of controller and memory system
Publication Date: 2022.03.08 SK HYNIX INC
  • US11269765B2 patent drawing
  • US11269765B2 patent drawing
  • US11269765B2 patent drawing

AI summary

Various embodiments generally relate to a semiconductor device, and more particularly, to an operating method of a controller and a memory system. In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device including a plurality of memory blocks may include: generating High Performance Booster (HPB) data based on Logical to Physical (L2P) map data and storing the HPB data into at least one empty page included in a first memory block; assigning a second memory block when a number of empty pages included in the first memory block becomes smaller than a threshold number; and migrating HPB data, which is selected according to a predetermined criterion among the HPB data stored in the first memory block, into the second memory block, wherein at least a part of the HPB data is cached into a memory of a host.