Controller IC Queue Auxiliary Notification for Interrupt Handling
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Solution Overview
Problem
Existing storage device control systems, particularly those conforming to the Universal Flash Storage (UFS) specification, face performance bottlenecks due to the need for software modules to individually check multiple submission queues (SQs), completion queues (CQs), and interrupt aggregation groups (IAGs) for interrupts, leading to inefficient interrupt handling and performance reduction.
Innovation Solution
A controller IC and associated method that utilize queue auxiliary notification information to store and provide specific queue notification data, allowing for the reading of run-time registers of only the relevant queues instead of all queues, thereby enhancing performance by reducing unnecessary checks and improving interrupt handling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software modules check all queues individually to determine interrupt sources, then complete interrupt coverage is achieved, but processing time increases and performance decreases
Solution Approach 1:
The patent segments the interrupt notification mechanism into two parts: a global queue notification register indicating whether any queue has an interrupt, and auxiliary notification registers for each queue indicating specific interrupt sources. This segmentation allows the software to first check the global register to determine if interrupt handling is needed, avoiding unnecessary individual queue checks when no interrupts are present, thus reducing processing time while maintaining complete interrupt detection coverage.
Solution Approach 2:
The patent implements preliminary action by having the hardware automatically set the auxiliary notification registers to indicate specific interrupt sources before the software needs to check the queues. This preliminary tagging of interrupt sources allows the software to directly identify which queues have interrupts without performing sequential checks, significantly reducing interrupt handling time while ensuring complete coverage.
2Measurement precision
If individual queue checking is performed for all queues, then accurate interrupt source identification is achieved, but the number of operations increases
Solution Approach 1:
The patent introduces auxiliary notification registers as intermediary structures between the queues and the software module. These registers act as mediators that automatically capture and indicate the specific interrupt sources, allowing the software to accurately identify interrupt sources through a single register read operation rather than performing multiple individual queue checks, thus improving both accuracy and efficiency.
Solution Approach 2:
The patent creates copies of interrupt status information in the auxiliary notification registers, which are updated by hardware based on the actual interrupt states of each queue. This copying mechanism allows the software to read pre-processed interrupt status information directly from the auxiliary registers, achieving accurate interrupt source identification with minimal operations and significantly improving handling efficiency.
3Reliability
If comprehensive queue monitoring is implemented, then no interrupt is missed, but system complexity increases
Solution Approach 1:
The patent segments the notification system into a global notification register and multiple auxiliary notification registers, each serving a specific function. The global register provides a quick overview of interrupt status, while auxiliary registers provide detailed source information. This segmented structure maintains reliable interrupt detection by ensuring both overall status and specific source information are available, while the modular design actually reduces complexity compared to requiring individual software checks of all queues.
Data Source
AI summary
A controller integrated circuit (IC) and a method for controlling a storage device for a host device to enhance overall performance are provided. The host device may include the controller IC, where the storage device is positioned outside the host device. The controller IC may include a plurality of first queues, a first queue notification register and a first queue auxiliary notification register, where each first queue of the first queues is arranged to queue first queue entries for being used to interact with the storage device. The first queue notification register may store first queue notification information for indicating whether any first queue of the plurality of first queues sends any first interrupt. The first queue auxiliary notification register may store first queue auxiliary notification information for indicating which first queue of the plurality of first queues is the any first queue that has sent the any first interrupt.