Controller Map Cache Linear Binary Search Hybrid

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Solution Overview

Problem

As memory system storage capacity increases, the time to search for the address of a memory block during a read operation also increases due to the growing number of memory devices and addresses, leading to inefficiencies in data retrieval.

Innovation Solution

A controller that manages a map cache using a combination of linear and binary tree methods to quickly search for data storage positions, employing a descriptor manager to generate and store descriptors in both linear and binary tree structures, and a map search engine to perform linear or binary searches based on cache status.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory system storage capacity increases, then storage capacity is improved, but search time for memory block address increases

Engineering Contradiction:
Improvestorage capacityVSAvoidsearch time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the address mapping data structure into two parts: a linear table for sequential access and a binary tree for hierarchical search. This segmentation allows the system to handle large storage capacities while maintaining efficient search performance by dividing the search space into manageable segments with different access patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a dynamic search strategy that adapts the search method based on the current state of the map cache. When the cache is small or cold, linear search is used; when the cache is large or hot, binary search is employed. This dynamic adaptation optimizes search time as the system evolves and memory capacity increases.

Inventive Principle:
Principle #15Dynamics

2Ease of manufacture

If linear search method is used, then implementation simplicity is improved, but search speed deteriorates

Engineering Contradiction:
Improveimplementation simplicityVSAvoidsearch speed
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent merges two search methods into a unified hybrid approach. The linear table provides simple implementation and good cache locality, while the binary tree structure provides faster search performance. By combining both structures and selectively using them based on cache status, the system achieves both implementation simplicity and search speed.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If binary search method is used, then search speed is improved, but implementation complexity increases

Engineering Contradiction:
Improvesearch speedVSAvoidimplementation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent performs preliminary organization of address mapping data into both linear and binary tree structures during the caching phase. This preliminary action prepares the data in advance for both search methods, so when a search is needed, the system can immediately choose the appropriate method without incurring complex processing overhead during the actual search operation.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If map cache is frequently updated, then data freshness is improved, but search efficiency deteriorates

Engineering Contradiction:
Improvedata freshnessVSAvoidsearch efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the search strategy parameter based on the update frequency and status of the map cache. When updates are frequent and the cache is small or inconsistent, linear search is used for simplicity and consistency. When updates are less frequent and the cache is large and stable, binary search is used for efficiency. This parameter adaptation maintains data freshness while optimizing search efficiency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11954041B2Controller including map cache and memory system including controller
Publication Date: 2024.04.09 SK HYNIX INC
  • US11954041B2 patent drawing
  • US11954041B2 patent drawing
  • US11954041B2 patent drawing

AI summary

The present technology includes a controller and a memory system including the same. The controller includes a descriptor manager configured to generate descriptors including logical addresses and physical addresses respectively mapped to the logical addresses, a map cache configured to store the descriptors in a linear structure and a binary tree structure, and a map search engine configured to search for a descriptor corresponding to a logical address received from an external device among the descriptors stored in the map cache by performing a linear search method, a binary search method, or both, according to a status of the map cache.