Controller Map Cache Management for Storage Devices

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Solution Overview

Problem

Storage devices face challenges in maximizing the hit ratio of a map cache with limited size, which affects the performance of the map table due to the need to manage both sequential and random data patterns efficiently.

Innovation Solution

Incorporating a pattern determination circuit, map cache management circuit, and entry eviction circuit in the controller to identify data patterns, selectively store target map table entries in the cache, and evict existing entries based on an eviction policy determined by input distribution or hit ratio analysis, thereby optimizing cache usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the map cache size is increased to improve hit ratio, then the map table performance is improved, but the device complexity and memory resource consumption increase

Engineering Contradiction:
Improvemap cache hit ratioVSAvoidcache management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic cache management by continuously monitoring access patterns and adjusting which map table entries are retained in the cache. The cache eviction policy dynamically adapts to changing data access patterns, evicting entries that are less likely to be accessed soon while retaining frequently accessed entries, thereby maintaining high hit ratios without requiring a large static cache size.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameters of cache management by using access pattern analysis to determine eviction priorities. Instead of using fixed eviction policies, the system varies the eviction parameters based on observed data patterns, such as sequential vs. random access patterns, to optimize cache performance for different workload characteristics.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If the map cache size is limited to reduce device complexity, then the device complexity is reduced, but the map cache hit ratio decreases

Engineering Contradiction:
Improvecache management complexityVSAvoidmap cache hit ratio
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system performs preliminary analysis of data access patterns to predict which map table entries will be accessed next. By proactively retaining these predicted entries in the cache before they are actually needed, the system increases the hit ratio of the limited cache size. This preliminary action allows the cache to be more effective without requiring additional cache memory.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If traditional cache eviction policies are used to manage limited cache size, then the cache management is simplified, but the map table performance is reduced

Engineering Contradiction:
Improvecache eviction simplicityVSAvoidmap table performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system implements feedback mechanisms by continuously monitoring cache hit ratios and access patterns, then using this feedback to adjust the eviction policy. When the cache hit ratio drops below a threshold, the system modifies its eviction behavior to retain more entries. This feedback loop allows the system to automatically optimize performance without complex manual configuration while maintaining simple operation.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11194737B2Storage device, controller and method for operating the controller for pattern determination
Publication Date: 2021.12.07 SK HYNIX INC
  • US11194737B2 patent drawing
  • US11194737B2 patent drawing
  • US11194737B2 patent drawing

AI summary

A controller suitable for controlling a semiconductor memory device includes a pattern determination circuit configured to determine a pattern information of data corresponding to a command received from a host. The controller includes a map cache management circuit configured to determine a target map table entry among map table entries of a map table based on the pattern information, and store, when the target map table entry does not exist in a map cache which stores some among the map table entries, the target map table entry in the map cache. The controller includes an entry eviction circuit configured to evict some among map table entries stored in the map cache, when storing the target map table entry in the map cache.