Controller Memory Abnormality Detection and Safety Interlock
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Solution Overview
Problem
Controllers face risks of data loss and abnormality due to power failures and electronic noise, particularly in volatile memory, leading to inappropriate control of controlling subjects when non-volatile memory also fails, causing safety issues.
Innovation Solution
A controller design with dual memory systems, where a volatile memory (SRAM) retains data during power supply and a non-volatile memory (EEPROM) serves as backup, with judging parts to detect abnormalities and prevent control based on faulty data, and a mechanism to prohibit idling stop control when memory abnormalities are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory is used for speedy control, then access speed is improved, but data loss occurs when electric power is suspended
Solution Approach 1:
The memory system is divided into two independent parts: volatile memory for speed-critical control operations and non-volatile memory for data retention. Each memory part has dedicated judging parts that independently evaluate its reliability, allowing the system to segment functionality based on performance requirements while maintaining overall system reliability through redundancy.
2Reliability
If non-volatile memory is used for data backup, then data retention is improved, but data abnormalities occur when memory breaks down
Solution Approach 1:
Judging parts continuously monitor the integrity of memory data by comparing read values against expected patterns and tracking write operations. When abnormalities are detected in either memory part, the feedback mechanism triggers protective actions such as prohibiting control operations, ensuring that faulty data does not lead to incorrect control decisions.
Solution Approach 2:
The system performs preliminary checks of memory integrity before using stored data for control operations. By detecting abnormalities in advance through the judging parts, the system can prevent the use of corrupted data without waiting for actual control failures to manifest.
3Reliability
If backup data is written to non-volatile memory, then data retention is improved, but control based on abnormal data occurs when both memories fail
Solution Approach 1:
The judging parts provide continuous feedback on data integrity to the control system. When abnormalities are detected in the backup memory or primary memory, the feedback mechanism activates protective measures that prohibit control operations based on potentially faulty data, preventing incorrect control decisions even when both memory systems are compromised.
Solution Approach 2:
The system establishes beforehand that control operations will be prohibited if memory abnormalities are detected, creating a safety cushion against incorrect control. This preventive measure ensures that even if both memories fail or contain abnormal data, the system does not execute potentially harmful control actions.
4Reliability
If multiple judging parts are added to detect abnormalities, then reliability is improved, but device complexity increases
Solution Approach 1:
The judging parts are integrated into the existing memory control architecture, serving multiple functions: validating data integrity, detecting abnormalities, and triggering protective controls. By making the judging mechanism multi-functional and embedded within the existing control flow, the system achieves enhanced reliability without proportionally increasing structural complexity.
Data Source
AI summary
A controller includes a first judging part that judges abnormality of a first memory part, and a second judging part that judges abnormality of a second memory part based on (1) results of comparing with each other data having a same content written in the second memory part multiple times, and (2) a total amount of the data read out from the second memory part, when the first memory part is judged to be abnormal. In addition, a third judging part judges abnormality of the second memory part, based on results of comparing the data written in the second memory part with the data read out from the second memory part.