Multi-Core Controller Wear Equalization via Dynamic Remapping
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Solution Overview
Problem
In data storage devices with multiple cores, uneven wear levels across storage regions lead to performance degradation due to non-uniform usage, as some cores experience higher Program/Erase (P/E) counts than others, causing imbalance in storage region wear.
Innovation Solution
A data storage device with a controller that includes a first CPU and a second CPU with multiple cores, which compares P/E average counts and performs remapping of logical block addresses to equalize wear levels by redistributing data across cores based on preset threshold differences in P/E counts and access counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data storage devices use multiple cores to increase processing capacity, then productivity is improved, but uneven wear levels across storage regions cause performance degradation
Solution Approach 1:
The system dynamically changes the mapping parameters between logical block addresses and physical cores based on real-time P/E count monitoring. When wear imbalance exceeds a threshold, the mapping relationships are adjusted to redistribute access patterns, thereby maintaining performance stability while utilizing multiple cores for high productivity
Solution Approach 2:
The controller implements a feedback mechanism that continuously monitors P/E counts of each core and adjusts the logical block address mapping accordingly. This closed-loop control ensures that wear is evenly distributed across all cores, preventing performance degradation while maintaining high processing capacity through multi-core operation
2Speed
If logical block addresses are mapped to specific cores, then access speed is improved, but uneven P/E counts cause wear imbalance
Solution Approach 1:
The logical block address to core mapping is made dynamic rather than static. The system periodically evaluates P/E counts and remaps logical block addresses to different cores based on current wear states. This dynamic adjustment maintains fast access speeds by keeping mapping relationships while adapting them to prevent wear imbalance
Solution Approach 2:
The mapping parameters between logical block addresses and physical cores are changed based on wear conditions. When P/E count differences exceed thresholds, the system modifies mapping relationships to redistribute access patterns, thereby maintaining access speed while achieving wear level uniformity across all cores
3Stability of the object's composition
If remapping operation is performed frequently to equalize wear, then wear level uniformity is improved, but loss of time increases
Solution Approach 1:
The system performs remapping operations proactively before severe wear imbalance occurs. By monitoring P/E counts continuously and triggering remapping when thresholds are approached, the system prevents extreme wear differences from developing, reducing the frequency and duration of remapping operations while maintaining wear uniformity
Solution Approach 2:
The system applies remapping selectively rather than continuously. Remapping is performed only when P/E count differences exceed predetermined thresholds, avoiding unnecessary remapping operations. This partial action approach maintains wear uniformity while minimizing time loss from remapping operations
Data Source
AI summary
A data storage device may include: a memory device; and a controller configured to control an operation of the memory device. The controller may include a first CPU and a second CPU including a plurality of cores, wherein the first CPU compares P/E (Program/Erase) average counts for the plurality of cores of the second CPU, and performs a remapping operation of changing a core which is mapped to logical block addresses received from a host.